8051 architecture question

I've been through a couple of 8051 tutorials but still have a very
fuzzy view of its architecture.

Could someone draw me a simple view of it.

From what I gather there is Program Memory and Data Memory. 

Withing Data Memory there are 

1) General Purpose Registers (arranged in banks)
2) Bit Addressable Registers
3) Stack Space
4) SFR (Special Function Registers)


Now are Program Memory and Data Memory 2 separate memory spaces?  If
not exactly where in Program memory does Data memory fit in?  I read
something about both these memories being dual mapped...  

Also where does the reserved memory area and scratchpad memory fit
into the picture.

Thanks.

JBrewster wrote:

> I've been through a couple of 8051 tutorials but still have a very
> fuzzy view of its architecture.
> 
> Could someone draw me a simple view of it.
> 
> From what I gather there is Program Memory and Data Memory. 
> 
> Withing Data Memory there are 
> 
> 1) General Purpose Registers (arranged in banks)
> 2) Bit Addressable Registers
> 3) Stack Space
> 4) SFR (Special Function Registers)
> 
> 
> Now are Program Memory and Data Memory 2 separate memory spaces?  If
> not exactly where in Program memory does Data memory fit in?  I read
> something about both these memories being dual mapped...  
> 
> Also where does the reserved memory area and scratchpad memory fit
> into the picture.
> 
> Thanks.

 google for "8051 memory", lots of info

JBrewster wrote:
> I've been through a couple of 8051 tutorials but still have a very
> fuzzy view of its architecture.
> 
> Could someone draw me a simple view of it.
> 
> From what I gather there is Program Memory and Data Memory. 
> 
> Withing Data Memory there are 
> 
> 1) General Purpose Registers (arranged in banks)
> 2) Bit Addressable Registers
> 3) Stack Space
> 4) SFR (Special Function Registers)
> 
> 
> Now are Program Memory and Data Memory 2 separate memory spaces? 

Yes, it can be easies to consider a vanilla romless device.
There, PSEN enables CODE memory, and WRN/RDN control the XRAM,
so there is a total of 128K, as 64K code and 64K XDATA.
That is also why there are distinct MOVC and MOVX opcodes.

In modern devices, mostly CODE is on-chip and XDATA can be
mapped onto on chip XRAM, and also on chip EEPROM.
The AT89C51ED2 is a good example of this.


  If
> not exactly where in Program memory does Data memory fit in?  I read
> something about both these memories being dual mapped...  
> 
> Also where does the reserved memory area and scratchpad memory fit
> into the picture.

They sound variant/vendor dependant, and are not C51 core specific.

-jg

JBrewster wrote:

> I've been through a couple of 8051 tutorials but still have a very
> fuzzy view of its architecture.
> 
> Could someone draw me a simple view of it.
> 
> From what I gather there is Program Memory and Data Memory.
> 
> Withing Data Memory there are
> 
> 1) General Purpose Registers (arranged in banks)
> 2) Bit Addressable Registers
> 3) Stack Space
> 4) SFR (Special Function Registers)
> 
> 
> Now are Program Memory and Data Memory 2 separate memory spaces? 

Completely separate. This it what is known as a Harvard architecture where
code and data spaces are kept quite separate. In the 8051 you can have up
to 64K of each.

Ian

Ian Bell wrote:
> JBrewster wrote:
>>Now are Program Memory and Data Memory 2 separate memory spaces? 
>  
> Completely separate. This it what is known as a Harvard architecture where
> code and data spaces are kept quite separate. In the 8051 you can have up
> to 64K of each.

Fully agree. Just want to add that one can map the mcu signals in a way 
that both code and external memory are the same. Many development kits 
do this by default to allow the user to "upload" code into the external 
data memory of which a certain part will appear as the code memory.
Coding wise this leads to a point where movc and movx will access the 
same memory location. However this breaks the Harvard paradigm (ofcourse).

just my 2c,
Matthias
-- 
Matthias Arndt <marndt@asmsoftware.de> <matthias.arndt@tu-clausthal.de>
PGP-Key: http://www.asmsoftware.de/marndt.pgp   ICQ: 40358321
 >>> Jabber: simonsunnyboy@jabber.ccc.de <<<

JBrewster wrote:
> I've been through a couple of 8051 tutorials but still have a very
> fuzzy view of its architecture.
> 
> Could someone draw me a simple view of it.
> 
> From what I gather there is Program Memory and Data Memory. 
> 
> Withing Data Memory there are 
> 
> 1) General Purpose Registers (arranged in banks)
> 2) Bit Addressable Registers
> 3) Stack Space
> 4) SFR (Special Function Registers)
> 
> 
> Now are Program Memory and Data Memory 2 separate memory spaces?  If
> not exactly where in Program memory does Data memory fit in?  I read
> something about both these memories being dual mapped...  
> 
> Also where does the reserved memory area and scratchpad memory fit
> into the picture.
> 
> Thanks.
> 

The answer is "it can be". You can either split the data and address
spaces, or join them. The processor becomes slightly harder to program
in its split configuration, for example, it is more difficult to load
constants from the code space if, for example, you place the rom there
and need to access that.

Most of the places I used (ok, all of them) used the 8051 as a
unified address architecture.

There are 3 memory spaces (without tricks and such)
1-Code 64K max
2-Extenal RAM  64K max
3-Internal RAM 256 Bytes Max
The internal RAM overlays the 128 bytes of Register Space.
It gets confusing here.  You get the full 256 bytes of internal RAM Plus
the registers. ( there are some overlapping instructions).
The 4 register banks are in the RAM. The bit space (256 bits) over lays
part of the RAM and Some of the register. (this allows you to use bit or
byte commands on them).

The reserved memory area  does nothing, it is extra space to add things
in the future.
scratchpad memory is a programming term not an 8051 memory space.
look at www.8052.com for more info.

"JBrewster" <john@fakeemail.com> wrote in message

> I've been through a couple of 8051 tutorials but still have a very
> fuzzy view of its architecture.
>
> Could someone draw me a simple view of it.

Assuming a basic 8051 (not a '52, no internal flash or whatever):

--
There is 64Kbyte of program space, and 64Kbyte of data space.
The program space is read-only and enabled by the CPU's #PSEN
line; the data space is read-write and enabled by the CPU's
#RD and #WR lines.

You can hold read-only constant data in program space, but you are limited
as to the instructions and/or addressing modes by which that
can be accessed. The assembler instructions used determine which
space to deal with: MOVX refers to data space, and MOVC refers
to program space.

There is, of course, nothing to stop you hardware mapping
the same physical memory (or a subset of it) so that it appears
in both data (MOVX) and code (MOVC) space.

--

The 8051 has 256 bytes of internal on-chip "memory", independent
from the 2*64K*8 mentioned above. However, only the bottom 128
bytes is actual memory (holding register banks, bit-addressable
memory, the stack, and everything else). The upper 128 bytes
is actual special function registers.

You gain access to this 256 bytes using yet more (different)
instructions. The upper 128 (the SFRs) can only be accessed
using direct addressing (no indirection)

--

The '52 variants (usually) have a real 256 bytes of internal
memory, in addition to the 128 bytes of SFRs, whose space they
overlap: when dealing with this upper 128 bytes, you use direct
addressing to get the SFRs and indirect addressing to get the
upper 128 bytes of real memory.

--

Then, there are processors which have onboard RAM which appears
as external RAM (in MOVX space). You use MOVX instructions
even though the RAM is physically on-chip: you have to set
config registers and/or hardware pins to select whether you
want addresses in the appropriate MOVX region to map to "real MOVX
RAM" or "internal MOVX RAM". Some processors will still generate
an external bus cycle even when dealing with onchip RAM in this
manner.

--

Most 8051 variants these days have onboard flash/otp/rom: this
internal ROM (in preference to accessing external MOVC space)
is selected using the #EA pin.

Richard [in PE12]

"Neil Kurzman" <nsk@mail.asb.com> wrote in message
news:427AFF65.EFE6844@mail.asb.com...

> 3-Internal RAM 256 Bytes Max
> The internal RAM overlays the 128 bytes of Register Space.
> It gets confusing here.  You get the full 256 bytes of internal RAM Plus
> the registers. ( there are some overlapping instructions).

On the plain 8051, you don't get the full 256 bytes internal RAM:
you get 128 RAM + 128 SFRs. It is only on the '52 architecture
that there is a full 256 bytes of internal RAM: the upper
128 bytes overlaying the SFRs (you use indirect or direct
addressing to disambiguate)

Richard [in PE12]

"Neil Kurzman" <nsk@mail.asb.com> wrote in message
news:427AFF65.EFE6844@mail.asb.com...

> 3-Internal RAM 256 Bytes Max
> The internal RAM overlays the 128 bytes of Register Space.
> It gets confusing here.  You get the full 256 bytes of internal RAM Plus
> the registers. ( there are some overlapping instructions).

On the plain 8051, you don't get the full 256 bytes internal RAM:
you get 128 RAM + 128 SFRs. It is only on the '52 architecture
that there is a full 256 bytes of internal RAM: the upper
128 bytes overlaying the SFRs (you use indirect or direct
addressing to disambiguate)

Richard [in PE12]