3.3V CMOS processor driving a device with Vih higher than processor Voh?

I need to drive a 5 volt ADC (LTC1863) to be able to use a 
Vref of 4.096 volts.  The Vih of the ADC is 2.4 volts.  The 
processor is a 3.3 volt xMOS with a Voh of 2.6 volts 
(measurements show it to be 3.1 volts with no load, but the 
processor spec. says 2.4 volts at 3.0 volts).  So I have a 
200 mV margin.  Anyone done something like this, and how 
reliable is it?

To get an idea of what I could do, I looked at the 
development kit schematics and saw that it was driving a 
PCA8550 I2C EEPROM.  The spec. says its Vih is 2.7 volts. 
Now how (or why) would someone develop a kit that seems to 
have a -100 mV margin?

Since I want the design to be reliable, I would really like 
to hear from some of you with design experience.


Thanks,
Dave

On Mon, 25 Jul 2005 20:22:11 GMT, the renowned Dave Boland
<NODARNSPAMdboland9@stny.rr.com> wrote:

>I need to drive a 5 volt ADC (LTC1863) to be able to use a 
>Vref of 4.096 volts.  The Vih of the ADC is 2.4 volts.  The 
>processor is a 3.3 volt xMOS with a Voh of 2.6 volts 
>(measurements show it to be 3.1 volts with no load, but the 
>processor spec. says 2.4 volts at 3.0 volts). 

Usually CMOS outputs swing very close to the power rails, with no
load. The only static load on your output is leakage currents. Are you
sure about the 3.1V measurement? Did you use a bench multimeter or a
scope? I'd be surprised if the difference is more than a couple of
tens of mV with no load. 

If it's a Z8 Encore! that you're working with , the 2.4V spec is with
a (relatively) massive 2mA load on the output. 

> So I have a 
>200 mV margin.  Anyone done something like this, and how 
>reliable is it?

It's commonly done and is reliable. The output swing is typically
essentially hard to the rails unless you've got something odd with
your processor, so 3.3 is a pretty good drive for a TTL high (2.4V
minimum). If the 3.3V device has CMOS-level or ST inputs, that's
another matter. 

The Vih and Vil of "TTL" level CMOS inputs change with supply voltage,
but not proportionally. When you have two entirely different supply
regulators, of course, you have to consider worst-case for both. 

>To get an idea of what I could do, I looked at the 
>development kit schematics and saw that it was driving a 
>PCA8550 I2C EEPROM.  The spec. says its Vih is 2.7 volts. 
>Now how (or why) would someone develop a kit that seems to 
>have a -100 mV margin?

SCL and SDA will be driven by an open-drain output with pullup to Vdd,
so the Voh on the datasheet doesn't really apply. 

Again, there are only leakage currents. Maximum input current (70&#4294967295;C)
is 12uA on SCL/SDA, so with a 10K pullup that will mean 120mV of drop
across the pullup resistor. You have to add any other leakages in your
circuit (probably just the output leakage on the micro) if you want to
check how much margin there is. 

>Since I want the design to be reliable, I would really like 
>to hear from some of you with design experience.
>
>
>Thanks,
>Dave




Best regards, 
Spehro Pefhany
-- 
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Spehro,

I used my trusty (??) Radio Shack DMM, but you are correct 
that most of the readings were very close to the Vdd of 3.3 
volts.  I like to take the worst case assumptions for a 
design because electrons (or software) don't wear rose 
colored glasses.

The processor is actually a eZ80 Acclaim (very good guess I 
might add!), but it will likely be similar to the Encore. 
Still, I like to use that worst case (well, within reason) 
concept to keep me out of trouble.

I forgot that the I2C is open collector (drain), so I should 
not have brought this into the discussion.  There are a 
number of other devices that have a Vih of 2.4 volts, and 
all are xMOS.  So it looks like a plan.

Thanks again Spehro!


Dave,

Spehro Pefhany wrote:
> On Mon, 25 Jul 2005 20:22:11 GMT, the renowned Dave Boland
> <NODARNSPAMdboland9@stny.rr.com> wrote:
> 
> 
>>I need to drive a 5 volt ADC (LTC1863) to be able to use a 
>>Vref of 4.096 volts.  The Vih of the ADC is 2.4 volts.  The 
>>processor is a 3.3 volt xMOS with a Voh of 2.6 volts 
>>(measurements show it to be 3.1 volts with no load, but the 
>>processor spec. says 2.4 volts at 3.0 volts). 
> 
> 
> Usually CMOS outputs swing very close to the power rails, with no
> load. The only static load on your output is leakage currents. Are you
> sure about the 3.1V measurement? Did you use a bench multimeter or a
> scope? I'd be surprised if the difference is more than a couple of
> tens of mV with no load. 
> 
> If it's a Z8 Encore! that you're working with , the 2.4V spec is with
> a (relatively) massive 2mA load on the output. 
> 
> 
>>So I have a 
>>200 mV margin.  Anyone done something like this, and how 
>>reliable is it?
> 
> 
> It's commonly done and is reliable. The output swing is typically
> essentially hard to the rails unless you've got something odd with
> your processor, so 3.3 is a pretty good drive for a TTL high (2.4V
> minimum). If the 3.3V device has CMOS-level or ST inputs, that's
> another matter. 
> 
> The Vih and Vil of "TTL" level CMOS inputs change with supply voltage,
> but not proportionally. When you have two entirely different supply
> regulators, of course, you have to consider worst-case for both. 
> 
> 
>>To get an idea of what I could do, I looked at the 
>>development kit schematics and saw that it was driving a 
>>PCA8550 I2C EEPROM.  The spec. says its Vih is 2.7 volts. 
>>Now how (or why) would someone develop a kit that seems to 
>>have a -100 mV margin?
> 
> 
> SCL and SDA will be driven by an open-drain output with pullup to Vdd,
> so the Voh on the datasheet doesn't really apply. 
> 
> Again, there are only leakage currents. Maximum input current (70&#4294967295;C)
> is 12uA on SCL/SDA, so with a 10K pullup that will mean 120mV of drop
> across the pullup resistor. You have to add any other leakages in your
> circuit (probably just the output leakage on the micro) if you want to
> check how much margin there is. 
> 
> 
>>Since I want the design to be reliable, I would really like 
>>to hear from some of you with design experience.
>>
>>
>>Thanks,
>>Dave
> 
> 
> 
> 
> 
> Best regards, 
> Spehro Pefhany

I do exactly this with LTC1860 and an Altera FPGA with no problems.

One issue that may or may not matter : In my circuit the ADC is "grounded" 
to my analog ground, whereas the digital I/O is driven/referemnce to digital 
ground. I doubt it matters, but I compensate for possible potential 
differences in the grounds with a tiny R-C (I think it was 10ohm and 10pf - 
C decoupling the signal to the input devices ground)

"Dave Boland" <NODARNSPAMdboland9@stny.rr.com> wrote in message 
news:TRbFe.175041$g5.74535@twister.nyroc.rr.com...
>I need to drive a 5 volt ADC (LTC1863) to be able to use a Vref of 4.096 
>volts.  The Vih of the ADC is 2.4 volts.  The processor is a 3.3 volt xMOS 
>with a Voh of 2.6 volts (measurements show it to be 3.1 volts with no load, 
>but the processor spec. says 2.4 volts at 3.0 volts).  So I have a 200 mV 
>margin.  Anyone done something like this, and how reliable is it?
>
> To get an idea of what I could do, I looked at the development kit 
> schematics and saw that it was driving a PCA8550 I2C EEPROM.  The spec. 
> says its Vih is 2.7 volts. Now how (or why) would someone develop a kit 
> that seems to have a -100 mV margin?
>
> Since I want the design to be reliable, I would really like to hear from 
> some of you with design experience.
>
>
> Thanks,
> Dave
> 

Gary,

This is similar to what I'm doing, except I don't plan on
using the RC to decouple.  I talked to the LTC applications
engineer and they suggested I consider the approach
discussed in the article below.

http://www.hottconsultants.com/techtips/split-gnd-plane.html

Dave,

Gary Pace wrote:

> I do exactly this with LTC1860 and an Altera FPGA with no problems.
> 
> One issue that may or may not matter : In my circuit the ADC is "grounded" 
> to my analog ground, whereas the digital I/O is driven/referemnce to digital 
> ground. I doubt it matters, but I compensate for possible potential 
> differences in the grounds with a tiny R-C (I think it was 10ohm and 10pf - 
> C decoupling the signal to the input devices ground)
> 
> "Dave Boland" <NODARNSPAMdboland9@stny.rr.com> wrote in message 
> news:TRbFe.175041$g5.74535@twister.nyroc.rr.com...
> 
>>I need to drive a 5 volt ADC (LTC1863) to be able to use a Vref of 4.096 
>>volts.  The Vih of the ADC is 2.4 volts.  The processor is a 3.3 volt xMOS 
>>with a Voh of 2.6 volts (measurements show it to be 3.1 volts with no load, 
>>but the processor spec. says 2.4 volts at 3.0 volts).  So I have a 200 mV 
>>margin.  Anyone done something like this, and how reliable is it?
>>
>>To get an idea of what I could do, I looked at the development kit 
>>schematics and saw that it was driving a PCA8550 I2C EEPROM.  The spec. 
>>says its Vih is 2.7 volts. Now how (or why) would someone develop a kit 
>>that seems to have a -100 mV margin?
>>
>>Since I want the design to be reliable, I would really like to hear from 
>>some of you with design experience.
>>
>>
>>Thanks,
>>Dave
>>
> 
> 
>