Q: lpc921 compatiblity with 8051?

hi,

I have a project with philips p89lpc921, and need to use it as standard 8051

now, this two chips have different clocks per cycle, as I understood,

so delay and timer do not work corectly


anyone knows how to make this work? i tried writing DIVM=3, 
but it didn't work

help please, I am out of ideas :o)


 

Petar Silic wrote:
> hi,
> 
> I have a project with philips p89lpc921, and need to use it as standard 8051
> 
> now, this two chips have different clocks per cycle, as I understood,
> 
> so delay and timer do not work corectly
> 
> 
> anyone knows how to make this work? i tried writing DIVM=3, 
> but it didn't work
> 
> help please, I am out of ideas :o)

  You need to get what Philips call a "Users Manual" - they split the
full info, with the Data Sheets having some, but the Instruction Set
( and all the cycle times ) are in the Users Manuals.
  In the LPC case, Philips use a 16 bit fetch, so most 2 byte opcodes
also execute in 1 CPU cycle. All jumps are 2 cycles, with no taken/not 
taken deltas.
-jg

Petar Silic wrote:
> hi,
>
> I have a project with philips p89lpc921, and need to use it as standard 8051
>
> now, this two chips have different clocks per cycle, as I understood,
>
> so delay and timer do not work corectly
>
>
> anyone knows how to make this work? i tried writing DIVM=3,
> but it didn't work
>
> help please, I am out of ideas :o)

Petar,

while the LPC900 family is clock cycle compatible which means that
every instruction takes 1/6 the time of a standard 12 clock 80C51,
timers are based on the input clock without any changes to a standard
51.  What you would like to do seems between very difficult and not
possible. I do not know your software but I hope you did not write
delay loops that are based on execution speed. If you use the same
timers on the LPC921 as you used on the 51, running at the same
frequency, the timer delays should be indentical.  However, your code
executes 6 times faster. This is a significant difference to other
cores from Dallas, Atmels new "single cycle" or Silabs which are not
cycle compatible. Their 3-4 clock cores or so called single cycle cores
will use a different number of cycles to execute an instruction that do
not scale from the original 80C51.

As a summary, the LPC921 core is fully compatible to the 8051 core, 6x
faster for any instruction. The timers are "even more compatible", no
changes required. This is great for most applications that used timers
for specific wait time for events to happen.  The code will be faster
and just waiting longer for the wait to finish. The only problem is
when programmers were counting instruction cycles to calculate delays,
the the relationship between CPU clock and timer clock does not work
any more.

btw. using DIVM slows down the clock to the whole chip, not just
peripherals.

An Schwob

An Schwob in the USA wrote:
> Petar Silic wrote:
> 
>>hi,
>>
>>I have a project with philips p89lpc921, and need to use it as standard 8051
>>
>>now, this two chips have different clocks per cycle, as I understood,
>>
>>so delay and timer do not work corectly
>>
>>
>>anyone knows how to make this work? i tried writing DIVM=3,
>>but it didn't work
>>
>>help please, I am out of ideas :o)
> 
> 
> Petar,
> 
> while the LPC900 family is clock cycle compatible which means that
> every instruction takes 1/6 the time of a standard 12 clock 80C51,

Not quite correct - see my other post, and the LPC users manuals.

> timers are based on the input clock without any changes to a standard
> 51.  What you would like to do seems between very difficult and not
> possible. I do not know your software but I hope you did not write
> delay loops that are based on execution speed.

If so, they will need to be re-tuned for the LPC opcodes.

  If you use the same
> timers on the LPC921 as you used on the 51, running at the same
> frequency, the timer delays should be indentical.  However, your code
> executes 6 times faster. This is a significant difference to other
> cores from Dallas, Atmels new "single cycle" or Silabs which are not
> cycle compatible. Their 3-4 clock cores or so called single cycle cores
> will use a different number of cycles to execute an instruction that do
> not scale from the original 80C51.

Always read the opcode/cycle info for the variant you are using, esp. if 
you are worried about the granular timings.

Besides what An mentions, some cores have jumps that vary taken/not 
taken; some have 16 bit fetch [Philips,ST]; some accelerate all 
peripherals x4/x6/x12, some only the core...

DIVM=6 would be a good first-guess place to get appx nominal C51 
timings, assuing the same clock in.

-jg

Jim Granville wrote:
> An Schwob in the USA wrote:
> > Petar Silic wrote:
> >
> >>hi,
> >>
> >>I have a project with philips p89lpc921, and need to use it as standard 8051
> >>
> >>now, this two chips have different clocks per cycle, as I understood,
> >>
> >>so delay and timer do not work corectly
> >>
> >>
> >>anyone knows how to make this work? i tried writing DIVM=3,
> >>but it didn't work
> >>
> >>help please, I am out of ideas :o)
> >
> >
> > Petar,
> >
> > while the LPC900 family is clock cycle compatible which means that
> > every instruction takes 1/6 the time of a standard 12 clock 80C51,
>
> Not quite correct - see my other post, and the LPC users manuals.
>
> > timers are based on the input clock without any changes to a standard
> > 51.  What you would like to do seems between very difficult and not
> > possible. I do not know your software but I hope you did not write
> > delay loops that are based on execution speed.
>
> If so, they will need to be re-tuned for the LPC opcodes.
>
>   If you use the same
> > timers on the LPC921 as you used on the 51, running at the same
> > frequency, the timer delays should be indentical.  However, your code
> > executes 6 times faster. This is a significant difference to other
> > cores from Dallas, Atmels new "single cycle" or Silabs which are not
> > cycle compatible. Their 3-4 clock cores or so called single cycle cores
> > will use a different number of cycles to execute an instruction that do
> > not scale from the original 80C51.
>
> Always read the opcode/cycle info for the variant you are using, esp. if
> you are worried about the granular timings.
>
> Besides what An mentions, some cores have jumps that vary taken/not
> taken; some have 16 bit fetch [Philips,ST]; some accelerate all
> peripherals x4/x6/x12, some only the core...
>
> DIVM=6 would be a good first-guess place to get appx nominal C51
> timings, assuing the same clock in.
>
> -jg

Jim,

as I really value your contributions very highly I would like to get a
pointer where you found differences in timing.  I compared chapter 16
of the LPC921 User Manual to the 8051 general instruction set as posted
on the Philips website with opcode length and cycles needed for
execution. They ALL match. Although I am very familiar with the LPC900
family I never heard that there was a different fetch than the regular
51.

I did look into the Manual and could absolutely not find what you were
referring to.  Is it possible that you actually mixed the LPC900 up
with some other device?

Also DIVM value is multiplied by two so DIVM=3 would do the job you
proposed. 

Schwob

Robertus wrote:

 > as I really value your contributions very highly I would like to get a
 > pointer where you found differences in timing.  I compared chapter 16
 > of the LPC921 User Manual to the 8051 general instruction set as posted
 > on the Philips website with opcode length and cycles needed for
 > execution. They ALL match. Although I am very familiar with the LPC900
 > family I never heard that there was a different fetch than the regular
 > 51.


I just grabbed a Usermanual, in this case the LPC915/6/7.
It shows SET/CLR/CPL bit opcodes as 2 byte / 1cycle, whilst my
Atmel ref shows 2 bytes 2 cycles on std C51...

I have not physically tested the silicon

 >
 > I did look into the Manual and could absolutely not find what you were
 > referring to.  Is it possible that you actually mixed the LPC900 up
 > with some other device?
 >
 > Also DIVM value is multiplied by two so DIVM=3 would do the job you
 > proposed.


oops, meant to say divide the external clk by 6...

-jg

Jim Granville wrote:
 > I just grabbed a Usermanual, in this case the LPC915/6/7.
 > It shows SET/CLR/CPL bit opcodes as 2 byte / 1cycle, whilst my
 > Atmel ref shows 2 bytes 2 cycles on std C51...

Oops - too many open documents & not enough care ....
The Generic C51 does execute these 2 byte opcodes in 1 cycle.
The STm newest core looks identical to the Philips LPC9xx,
and the timing seems deliberate [Some 2 byte opcodes that they _could_ 
have made 1 cycle, have been kept at 2 cycles ?].

The LP2052 has a byte wide, single cycle fetch, so it needs 2 cycles
for any 2 byte opcode.

-jg

An Schwob in the USA <schwobus@aol.com> wrote:

> while the LPC900 family is clock cycle compatible which means that
> every instruction takes 1/6 the time of a standard 12 clock 80C51,
> timers are based on the input clock without any changes to a standard
> 51.  What you would like to do seems between very difficult and not


no , I think timers run on 1/2 oscilator freq on lpc921,
on 8051 they run on 1/12 osc.freq


so if I speed down clock by 6 times I get 8051

still stuff doesn't work :o)

In article <dehl61$sb4$1@bagan.srce.hr>, Petar Silic
<shilla@fly.srk.fer.hr> writes
>
>hi,
>
>I have a project with philips p89lpc921, and need to use it as standard 8051
>
>now, this two chips have different clocks per cycle, as I understood,
>
>so delay and timer do not work corectly

The timers DO work correctly. 

The standard 51 family use 12 clocks per cycle
Dalas-Maxim use 4 clocks per cycle
Infineon, Temic, Atmel, Philps Cygnal, Sylicon labs etc etc etc use 6
clock per cycle

Some Dallas, Infineon, Philips and others use 2 clocks per cycle for
some parts.

There are VERY FEW still using the 12 clocks per cycle these days.  Many
like the Philips, Atmel and Infineon let you set5 the part in either 6
or 12 cycles but I don't thing this wil continue much longer.

BTW I don't think Intel even do a 51 now


RTFM is the answer to most of the questions you have.

-- 
\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
\/\/\/\/\ Chris Hills  Staffs  England     /\/\/\/\/
/\/\/ chris@phaedsys.org      www.phaedsys.org \/\/\
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