I'm interested to know if anyone has successfully programmed a Xilinx
XC9500XL CPLD with a PIC18F using the Xilinx JTAG/TAP port. I've been
reading Xilinx app note 058 and it looks feasible. The inbound data stream
(SVF or XSVF file) would be coming into the PIC18F via a USB connection.
This is for the purposes of occasional field-upgrades, not the frequent
reconfigurations you would have with an FPGA using the USB & PIC combination
to eliminate its boot PROM.
Reply by jyaron●November 2, 20052005-11-02
It's possible. Been doing it for years.
However, still using Foundation 3.1i because the .svf file generated is a
reasonable size. I load the .xvf image into the uC flash memory then
launch the JTAG flash routine.
Did an .xvf to .h (Const data) translator in Delphi to link to HiTech-18