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Memory Suggestions

Started by Gromer November 24, 2005
Hi,

I have one basic doubt on how MEMORY WR/RD# cycles are emulated.. (i.e
memory read & write cycles emulated in software)..

How is the Assertion/Deassertion of WR/RD pins taken care (emulated) in
software whenever a memory address is being deferenced.

Thanks

Gromer wrote:
> Hi, > > I have one basic doubt on how MEMORY WR/RD# cycles are emulated.. (i.e > memory read & write cycles emulated in software).. > > How is the Assertion/Deassertion of WR/RD pins taken care (emulated) in > software whenever a memory address is being deferenced.
Simple, you don't have to worry about it. That's too low level for a CPU emulator. Yousuf Khan
As noted, this is very low level. Indeed, it depends on the type of
memory (DDR SDRAM, SDRAM,  Sync Flash/ROM/SRAM, Async devices) and even
then the requirements can vary greatly (that's one reason why memory
controllers have so many settable parameters).

Why do you ask?

Cheers

PeteS