Battery-backed RAM

Hi Everyone

I'm designing a system which uses low power SRAM powered by battery as
a backup device. The data sheet states that all I/Os mus be kept within

0.2V of either Vcc or GND for the standby current to be guaranteed.
This is no surprise, one CMOS device must be held firmly in the off
state.


The I/Os will be connected to a powered down CMOS buffer while in
standby mode, and my question is: will the powered down buffer have
enough leakage current hold the I/Os at ground potential, or should I
provide weak pull-down resistors to prevent these pins from floating
above 0.2V? 


TIA 
Cheers 
Geoff

If nothing drives the bus the leakage current can be either
direction and could theoretically drive the bus to mid-voltages,
although in a similar to your practical scenario I have never seen
that.
A possible workaround to avoid all the resistors is to wake up
the system once every few seconds briefly and drive the bus down,
this should take care of it except perhaps at very high temperatures
which may or may not be an issue for you.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


Geoffrey wrote:
> Hi Everyone
>
> I'm designing a system which uses low power SRAM powered by battery as
> a backup device. The data sheet states that all I/Os mus be kept within
>
> 0.2V of either Vcc or GND for the standby current to be guaranteed.
> This is no surprise, one CMOS device must be held firmly in the off
> state.
>
>
> The I/Os will be connected to a powered down CMOS buffer while in
> standby mode, and my question is: will the powered down buffer have
> enough leakage current hold the I/Os at ground potential, or should I
> provide weak pull-down resistors to prevent these pins from floating
> above 0.2V? 
> 
> 
> TIA 
> Cheers 
> Geoff

Geoffrey wrote:

> Hi Everyone
> 
> I'm designing a system which uses low power SRAM powered by battery as
> a backup device. The data sheet states that all I/Os mus be kept within
> 
> 0.2V of either Vcc or GND for the standby current to be guaranteed.
> This is no surprise, one CMOS device must be held firmly in the off
> state.
> 
> 
> The I/Os will be connected to a powered down CMOS buffer while in
> standby mode, and my question is: will the powered down buffer have
> enough leakage current hold the I/Os at ground potential, or should I
> provide weak pull-down resistors to prevent these pins from floating
> above 0.2V? 
> 
> 
> TIA 
> Cheers 
> Geoff
> 
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