Atmel ARM AT91RM9200 SDRAM Issue

It appears that the SDRAM controller built into Atmel's AT91RM9200 ARM
9 chip only supports a burst length of 1.

Exactly what use is an SDRAM burst with a length of 1?  What advantage
does it have over an ordinary (non-burst) SDRAM access?

Ulf, are you there?

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> It appears that the SDRAM controller built into Atmel's AT91RM9200 ARM
> 9 chip only supports a burst length of 1.
>
> Exactly what use is an SDRAM burst with a length of 1?  What advantage
> does it have over an ordinary (non-burst) SDRAM access?
>
> Ulf, are you there?
>


Do you mean that it does one asynchronous cycle and the only read one
additional word in the burst?
The burst length is not configurable by the user, for sure.
Did not check in the oscilloscope (dont have one) but the burst length
should be
dependent on the bus master inside the chip.
The PDC does not use burst, and I think there should be FIFOs in the PDC.

One would think that you would burst at least one cache line,
but comments from the at91 support team indicates however that you are
correct.

-- 
Best Regards,
Ulf Samuelsson   ulf@a-t-m-e-l.com
This is a personal view which may or may not be
share by my Employer Atmel Nordic AB

"Ulf Samuelsson" ...
> > It appears that the SDRAM controller built into Atmel's AT91RM9200 ARM
> > 9 chip only supports a burst length of 1.
> >
> > Exactly what use is an SDRAM burst with a length of 1?  What advantage
> > does it have over an ordinary (non-burst) SDRAM access?
> >
> > Ulf, are you there?
>
> Do you mean that it does one asynchronous cycle and the only read one
> additional word in the burst?
> The burst length is not configurable by the user, for sure.
> Did not check in the oscilloscope (dont have one) but the burst length
> should be
> dependent on the bus master inside the chip.
> The PDC does not use burst, and I think there should be FIFOs in the PDC.
>
> One would think that you would burst at least one cache line,
> but comments from the at91 support team indicates however that you are
> correct.


Ulf,

I've used other ARM-cored chips (NetSilicon Net+ARM) that specified a "one
cycle write burst".

When asked, the supplier explained that, after the burst transfer mode is
entered, on each write cycle WITHIN THE SAME PAGE the lower bits of the
address are supplied by the CPU (much like the good old 'page mode DRAM').
Thus, it kept doing "single cycle" accesses as long as the transfer was
within the same page.
That explanation, with some study, fits the description in the SDRAM
datasheets.

Maybe this is the same with the Atmel?

Regards,
Arie de Muynck

"Arie de Muynck" <send.spam.to@spammer.org> skrev i meddelandet
news:4194ecb4$0$78753$e4fe514c@news.xs4all.nl...
> "Ulf Samuelsson" ...
> > > It appears that the SDRAM controller built into Atmel's AT91RM9200 ARM
> > > 9 chip only supports a burst length of 1.
> > >
> > > Exactly what use is an SDRAM burst with a length of 1?  What advantage
> > > does it have over an ordinary (non-burst) SDRAM access?
> > >
> > > Ulf, are you there?
> >
> > Do you mean that it does one asynchronous cycle and the only read one
> > additional word in the burst?
> > The burst length is not configurable by the user, for sure.
> > Did not check in the oscilloscope (dont have one) but the burst length
> > should be
> > dependent on the bus master inside the chip.
> > The PDC does not use burst, and I think there should be FIFOs in the
PDC.
> >
> > One would think that you would burst at least one cache line,
> > but comments from the at91 support team indicates however that you are
> > correct.
>
>
> Ulf,
>
> I've used other ARM-cored chips (NetSilicon Net+ARM) that specified a "one
> cycle write burst".
>
> When asked, the supplier explained that, after the burst transfer mode is
> entered, on each write cycle WITHIN THE SAME PAGE the lower bits of the
> address are supplied by the CPU (much like the good old 'page mode DRAM').
> Thus, it kept doing "single cycle" accesses as long as the transfer was
> within the same page.
> That explanation, with some study, fits the description in the SDRAM
> datasheets.
>
> Maybe this is the same with the Atmel?
>
> Regards,
> Arie de Muynck
>

Everyone is limited by whatever ARM has decided, and if their core does
not generate burst requests, then is it hard for the bus interface to
implement it.
Did not read that part of the ARM920T datasheet.
I think the burst is more important on read though.


-- 
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.