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little help with i2c

Started by Attila Csosz June 5, 2006
Hi,

I have a question in the i2c protocol. When the slave or the master 
sends a data byte the line state will hold the last bit state? For 
example I send a byte containing "0x01" it means the last bit is "1". 
The sda line will hold this value ( "1" ) or will be pulled down in the 
beginning in the next clock cycle?

Thanks
  Attila
Attila Csosz wrote:
> Hi, > > I have a question in the i2c protocol. When the slave or the master > sends a data byte the line state will hold the last bit state? For > example I send a byte containing "0x01" it means the last bit is "1". > The sda line will hold this value ( "1" ) or will be pulled down in the > beginning in the next clock cycle? > > Thanks > Attila
After the last data bit is sent, the receiver sends a 0 (ACK) or 1 (!ACK). Regards, Bruce
Attila Csosz <csosz33_AT@chello.hu> wrote:
> Hi, > > I have a question in the i2c protocol. When the slave or the master > sends a data byte the line state will hold the last bit state? For > example I send a byte containing "0x01" it means the last bit is "1". > The sda line will hold this value ( "1" ) or will be pulled down in the > beginning in the next clock cycle?
All implementations I have seen returned both the clock and data lines to high-impedance state after a transaction. -- :wq ^X^Cy^K^X^C^C^C^C
Ico schreef:
> Attila Csosz <csosz33_AT@chello.hu> wrote: >> Hi, >> >> I have a question in the i2c protocol. When the slave or the master >> sends a data byte the line state will hold the last bit state? For >> example I send a byte containing "0x01" it means the last bit is "1". >> The sda line will hold this value ( "1" ) or will be pulled down in the >> beginning in the next clock cycle? > > All implementations I have seen returned both the clock and data lines > to high-impedance state after a transaction. >
When there is more then one master on the bus, both clock and data lines should be high-impedance when idle. When there is only one master it is save to drive the clock line high between transactions.
Ico wrote:
> Attila Csosz <csosz33_AT@chello.hu> wrote: >> Hi, >> >> I have a question in the i2c protocol. When the slave or the master >> sends a data byte the line state will hold the last bit state? For >> example I send a byte containing "0x01" it means the last bit is "1". >> The sda line will hold this value ( "1" ) or will be pulled down in the >> beginning in the next clock cycle? > > All implementations I have seen returned both the clock and data lines > to high-impedance state after a transaction. >
That is the idle state. You normally leave the bus idle when you are not using it.
Attila Csosz wrote:
> Hi, > > I have a question in the i2c protocol. When the slave or the master > sends a data byte the line state will hold the last bit state? For > example I send a byte containing "0x01" it means the last bit is "1". > The sda line will hold this value ( "1" ) or will be pulled down in the > beginning in the next clock cycle?
A data value is never "held" on the data bus. I2C has a protocol that uses relative timing of transitions on the two signals to indicate the start and stop of a transfer as well as the clocking of the data. As others have said, after the data is sent, an acknowledge is returned from the receiver. This requires that the data sender release the SDA line and let the data receiver transmit the acknowledge.
Attila Csosz wrote:
> Hi, > > I have a question in the i2c protocol. When the slave or the master > sends a data byte the line state will hold the last bit state? For > example I send a byte containing "0x01" it means the last bit is "1". > The sda line will hold this value ( "1" ) or will be pulled down in the > beginning in the next clock cycle?
You are talking about a clock to clock basis rather than at the end of a byte I guess. The I2C spec says that the data should never change during a clock bit high as any such transition is interpreted as a start or stop. The data can change after the clock is brought low but must be ready before the next clock high. A somewhat rough timing diagram shows that the data can change somewhere between the clock highs. With all clocked data systems there are metastable conditions that arise if minimum setup and hold times are not observed. SCL ______|-------|________|--------|______ SDA xxDDDDDDDDDDDDDxxxxDDDDDDDDDDDDDDxxx *Peter*