I use Cypress EZ-USB FX2 for a data transmit system, FX2 in Slave FIFO mode, with FPGA as the master. I write proogram to transmit data from the PC to FX2.(direc is OUT) The problem is , when I set IFCONFIG = 0xC3 in firmware, which means Slave FIFOs executes on internal 48MHz clk source, it works well. but I need to set IFCONFIG = 0x43, which means Slave FIFOs executes on external clk source provied by FPGA through IFCLK pin, in this case, I can not write data into FX2. why ? 6MHz clock already sent to the IFCLK pin.
About EZ-USB FX2 Using external clock
Started by ●July 6, 2006
Reply by ●July 6, 20062006-07-06
is there an alternate configuration register which yuo need to touch to enable clock in on that pin? <wwxbei@gmail.com> wrote in message news:1152189548.007957.148470@b68g2000cwa.googlegroups.com...>I use Cypress EZ-USB FX2 for a data transmit system, FX2 in Slave > FIFO mode, with FPGA as the master. I write proogram to transmit data > from the PC to FX2.(direc is OUT) > The problem is , when I set IFCONFIG = 0xC3 in firmware, which means > Slave FIFOs executes on internal 48MHz clk source, it works well. but I > need to set IFCONFIG = 0x43, which means Slave FIFOs executes on > external clk source provied by FPGA through IFCLK pin, in this case, I > can not write data into FX2. why ? 6MHz clock already sent to the > IFCLK pin. >
Reply by ●July 10, 20062006-07-10
Bad luck on entering a nightmare world. For example, you need a clock
running to initialise Port D so your clock must be up. Because the FX2 chip
can be running (powered from the USB bus) before our hardware was running
(as indicated by HuskyIsReady), we had to be careful about when to
initialise things. FWIW, I ended up with the following messy code:
#define HUSKY_IS_READY ((IOE & 4) ? 1 : 0)
...
//
// We need Port E to see if Husky is ready.
//
PORTECFG = 0; // no alternate signals
IFCONFIG &= ~bmGSTATE; // GSTATE is false so it does not relay GPIF
signals to Port E
OEE = ((1<<0)+(1<<6)+(1<<7)); // Port E: Bits 0, 6, and 7 are output
IOE = (1<<6); // 28 November, 2005: Set Husky Reset off, UserLamp2 off
(inverted)
...
//
// Task Dispatcher: Main Loop
//
for(;;)
{
if ( ! HaveCalled_TD_Init && HUSKY_IS_READY )
{
//
// Husky has just come ready.
//
// Initialize user device.
//
// This uses HuskyIsReady to choose the internal or external clock so
Port D can be initialised.
// External clock = HuskyIsReady
//
HuskyIsReady = TRUE;
TD_Init();
HaveCalled_TD_Init = TRUE;
//
// Now we can setup IO Port D.
//
OED = ~0; // Port D is output
IOD = 0; // 28 November, 2005: All lamps off
ReportRegisters();
while (UartBusy())
;
}
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
SYNCDELAY;
//
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
EP1OUTCFG = 0xA0;
SYNCDELAY;
EP1INCFG = 0xA0;
SYNCDELAY;
#define VALID (1<<7)
#define INVALID (0<<7)
#define IN (1<<6)
#define OUT (0<<6)
#define BULK (2<<4)
#define B1024 (1<<3)
#define B512 (0<<3)
#define QUAD (0<<0)
#define TRIPLE (3<<0)
#define DOUBLE (2<<0)
//
// EP2
//
EP2CFG = VALID + OUT + BULK + B512 + QUAD;
SYNCDELAY;
// IFCLKOE = 0 / Don't care (but don't drive)
// IFCLKPOL = 0 // Don't care
// ASYNC = 0 // Synchronous
// GSTATE = 0 // We use Port E
// IFCGF01 = 3 // External Master
//
if ( HuskyIsReady )
IFCONFIG = bmIFCFG1 + bmIFCFG0; // IFCLKSRC = 0 (Extern clock source),
external master
else
IFCONFIG = bmIFCLKSRC + bm3048MHZ + bmIFCFG1 + bmIFCFG0; // IFCLKSRC =
1 (intern clock source), 48 MHz, external master
SYNCDELAY;
//
//
http://tightlink.cypress.com/TLService/XKBase?op=dispart&cid=30020&catId=293727682&artId=310860771
// says do this after.
//
REVCTL |= bmNOAUTOARM + bmSKIPCOMMIT;
SYNCDELAY;
SYNCDELAY;
FIFORESET = 0x80; // Reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
//
// Out endpoints do not come up armed
// EP2 is quad buffered
//
#if defined(SOFTWARE_LOOPBACK) || defined(SOFTWARE_COMMIT_OUT)
EP2BCL = 0x80; // re(arm) EP2OUT
SYNCDELAY;
EP2BCL = 0x80; // re(arm) EP2OUT
SYNCDELAY;
EP2BCL = 0x80; // re(arm) EP2OUT
SYNCDELAY;
EP2BCL = 0x80; // re(arm) EP2OUT
SYNCDELAY;
#else // AUTOOUT
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
#endif
//
// Make sure of an AUTOOUT 0->1 transition, if AUTOUT is used, even though
REVCTL.1 is true now.
//
EP2FIFOCFG = 0; // AUTOOUT=0, AUTOIN=0, ZEROLENIN=0, WORDWIDE=0
SYNCDELAY;
ASSERT(EP2FIFOCFG == 0);
#if defined(SOFTWARE_LOOPBACK)
EP2FIFOCFG = 0; // AUTOOUT=0, AUTOIN=0, ZEROLENIN=0, WORDWIDE=0
SYNCDELAY;
ASSERT(EP2FIFOCFG == 0);
#elif defined(SOFTWARE_COMMIT_OUT)
EP2FIFOCFG = 0; // AUTOOUT=0, AUTOIN=0, ZEROLENIN=0, WORDWIDE=0
SYNCDELAY;
ASSERT(EP2FIFOCFG == 0);
#else
EP2FIFOCFG = bmAUTOOUT; // AUTOOUT=1, AUTOIN=0, ZEROLENIN=0, WORDWIDE=0
SYNCDELAY;
ASSERT(EP2FIFOCFG == bmAUTOOUT);
#endif
PINFLAGSAB = 0;
SYNCDELAY;
PINFLAGSCD = 0;
SYNCDELAY;
//
// EP4 is not used..
//
EP4CFG = INVALID;
SYNCDELAY;
EP4FIFOCFG = 0; // Not word wide
SYNCDELAY;
//
// EP6 is used
//
EP6CFG = VALID + IN + BULK + B512 + QUAD;
SYNCDELAY;
FIFORESET = 0x80; // Reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
#if defined(SOFTWARE_LOOPBACK)
EP6FIFOCFG = bmZEROLENIN; // AUTOOUT=0, AUTOIN=0, ZEROLENIN=1,
WORDWIDE=0
SYNCDELAY;
ASSERT(EP6FIFOCFG == bmZEROLENIN);
#else
EP6FIFOCFG = bmAUTOIN + bmZEROLENIN; // AUTOOUT=0, AUTOIN=1, ZEROLENIN=1,
WORDWIDE=0
SYNCDELAY;
ASSERT(EP6FIFOCFG == bmAUTOIN + bmZEROLENIN);
#endif
SYNCDELAY;
EP6AUTOINLENH = (512) >> 8; // Auto-commit 512 byte packets
SYNCDELAY;
EP6AUTOINLENL = (512) & 0xFF; // Auto-commit 512 byte packets
SYNCDELAY;
//
// EP8 is not used..
//
EP8CFG = INVALID;
SYNCDELAY;
EP8FIFOCFG = 0; // Not word wide
SYNCDELAY;
#undef VALID
#undef INVALID
#undef IN
#undef OUT
#undef BULK
#undef B1024
#undef B512
#undef QUAD
#undef TRIPLE
#undef DOUBLE
// enable dual autopointer feature
AUTOPTRSETUP |= 0x7;
SYNCDELAY;
EnableRemoteWakeUp = TRUE; // Enable remote-wakeup
}
<wwxbei@gmail.com> wrote in message
news:1152189548.007957.148470@b68g2000cwa.googlegroups.com...
>I use Cypress EZ-USB FX2 for a data transmit system, FX2 in Slave
> FIFO mode, with FPGA as the master. I write proogram to transmit data
> from the PC to FX2.(direc is OUT)
> The problem is , when I set IFCONFIG = 0xC3 in firmware, which means
> Slave FIFOs executes on internal 48MHz clk source, it works well. but I
> need to set IFCONFIG = 0x43, which means Slave FIFOs executes on
> external clk source provied by FPGA through IFCLK pin, in this case, I
> can not write data into FX2. why ? 6MHz clock already sent to the
> IFCLK pin.
>
Reply by ●November 3, 20082008-11-03
>I use Cypress EZ-USB FX2 for a data transmit system, FX2 in Slave >FIFO mode, with FPGA as the master. I write proogram to transmit data >from the PC to FX2.(direc is OUT) >The problem is , when I set IFCONFIG = 0xC3 in firmware, which means >Slave FIFOs executes on internal 48MHz clk source, it works well. but I >need to set IFCONFIG = 0x43, which means Slave FIFOs executes on >external clk source provied by FPGA through IFCLK pin, in this case, I >can not write data into FX2. why ? 6MHz clock already sent to the >IFCLK pin. > >An earlier post "welcome to a nightmare world" just about sums it up with the cypresss FX2 well-known weakness in monitoring capability which reduces us to "debug by LED flashing". In our case we wanted to use port D as output port pins and not as FD15-8. So we followed the instructions to set all WORDWIDE=0 in the EPxFIFOCFG and got no output on port D! The solution was to ensure that the IFCLK input to the slave fifos was actually driven from the internal source, at least for a cycle. In our system, it is driven from a CPLD which is in turn clocked from CLKOUT. But if the CPLD is not programmed yet (e.g. during firmware development) it doesn't provide IFCLK. This is enough to prevent port D from becoming GPIO. Also FWIW, here is our TD_Init void TD_Init(void) // Called once at startup { // set the CPU clock to 48MHz //CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ; CPUCS = 0x12 ; // 1_0010 : CLKSP1:0=10, cpu clockspeed 48MHz, drive CLKOUT output pin 100 which clocks CPLD /* (from raphael berner: the clocking is as follows: the fx2 clockes the CPLD by the CLKOUT pin (pin 100), and the CPLD clocks the fifointerface on IFCLK, so in the firmware you should select external clocksource in the FX2 for the slave FIFO clock source. */ IOC = 0x00; IOA = 0x00; IOE= 0x00; // set port output default values - enable them as outputs next OEA = 0x8b; // 1000_1011. PA7 LED, PA3: nResetCPLD, PA1: runCPLD, PA0: tsReset // port B is used as FD7-0 for 8 bit FIFO interface to CPLD OEC = 0x0F; // now are cochlea and offchip DAC controls, before was 0000_1101 // JTAG, timestampMode, timestampTick, timestampMaster, resetTimestamp OED = 0xFF; // all bit addressable outputs, all WORDWIDE=0 so port d should be enabled OEE = 0xFF; // all outputs, byte addressable // set the slave FIFO interface to 30MHz, slave fifo mode // select slave FIFO mode with with FIFO clock source as external clock (from CPLD). // if the CPLD is not programmed there will not be any FIFO clock! // if there is no IFCLK then the port D pins are never enabled as outputs. // start with internal clock, switch to external CPLD clock source at end of TD_Init SYNCDELAY; IFCONFIG = 0xA3; // 1010_0011 // internal clock, 30MHz, drive clock IFCLKOE, slave FIFO mode SYNCDELAY; // may not be needed // disable interrupts by the input pins and by timers and serial ports. timer2 scanner interrupt enabled when needed from vendor request. IE &= 0x00; // 0000_0000 // disable interrupt pins 4, 5 and 6 EIE &= 0xE3; // 1110_0011; // Registers which require a synchronization delay, see section 15.14 // FIFORESET FIFOPINPOLAR // INPKTEND OUTPKTEND // EPxBCH:L REVCTL // GPIFTCB3 GPIFTCB2 // GPIFTCB1 GPIFTCB0 // EPxFIFOPFH:L EPxAUTOINLENH:L // EPxFIFOCFG EPxGPIFFLGSEL // PINFLAGSxx EPxFIFOIRQ // EPxFIFOIE GPIFIRQ // GPIFIE GPIFADRH:L // UDMACRCH:L EPxGPIFTRIG // GPIFTRIG //disable all ports A,C,E alternate functions SYNCDELAY; PORTCCFG = 0x00; SYNCDELAY; PORTACFG = 0x00; // do not use interrupts 0 and 1 SYNCDELAY; PORTECFG = 0x00; EP1OUTCFG = 0x00; // EP1OUT disabled SYNCDELAY; EP1INCFG = 0xA0; // 1010 0000 VALID+Bulk EP1IN enabled, bulk SYNCDELAY; EP2CFG = 0x00; // EP2 disabled SYNCDELAY; EP4CFG = 0x00; // EP4 disabled SYNCDELAY; EP6CFG = 0xE0; // EP6 enabled, in bulk, quad buffered SYNCDELAY; EP8CFG = 0x00; // EP8 disabled SYNCDELAY; REVCTL= 0x03; SYNCDELAY; FIFORESET = 0x80; SYNCDELAY; FIFORESET = 0x06; SYNCDELAY; FIFORESET = 0x00; SYNCDELAY; EP6AUTOINLENH=0x02; SYNCDELAY; EP6AUTOINLENL=0x00; SYNCDELAY; EP6FIFOCFG = 0x08 ; //0000_1000, autoin=1, wordwide=0 to automatically commit packets and make this an 8 bit interface to FD SYNCDELAY; EP2FIFOCFG = 0x00 ; // wordwide=0 SYNCDELAY; EP4FIFOCFG = 0x00 ; SYNCDELAY; EP8FIFOCFG = 0x00 ; //set FIFO flag configuration: FlagB: EP6 full, flagC and D unused SYNCDELAY; PINFLAGSAB = 0xE8; // 1110_1000 SYNCDELAY; cycleCounter=0; // missedEvents=0xFFFFFFFF; // one interrupt is generated at startup, maybe some cpld registers start in high state LED=1; // turn on LED clock=1; bitIn=0; latch=1; powerDown=0; // init biasgen ports and pins EZUSB_InitI2C(); // init I2C to enable EEPROM read and write initDAC(); JTAGinit=TRUE; IT0=1; // make INT0# edge-sensitive EX0=0; // do not enable INT0# IT1=1; // INT1# edge-sensitve EX1=0; // do not enable INT1# // timer2 init for scanner clocking in continuous mode T2CON=0x00; // 0000 0100 timer2 control, set to 16 bit with autoreload, timer stopped RCAP2L=0x00; // timer 2 low register loaded from vendor request. RCAP2H=0xFF; // starting reload values, counter counts up to 0xFFFF from these and generates interrupt when count rolls to 0 ET2=0; // disable interrupt to start toggleVReset(); // now switch to external IFCLK for FIFOs SYNCDELAY; // may not be needed IFCONFIG = 0x23; // 0010_0011 // extenal clock, slave fifo mode SYNCDELAY; // may not be needed }
