SPI problem - newbie - interfacing between two philips micros

hi all,
i m interfacing my philips micro sdk lpc936(slave) wid philips arm
micro sdk lpc2138(master).i m sending seven segment pattern thru master
.the slave pin SS is connected to one port pin of master thet provides
it logic high to select  it as slave.
do need to check the status of SS pin on slave side periodically
between byte transfers?
i m doing this wid polling on master side & interrupt driven on slave
side.

i hav configured master spiclk as cclk/31 (58.5895/31.33 = 1.843MHz) &
of slave as cclk/4 (7.373/4 =  1.843MHz) .do i need to consider
anything else for spiclk.

however do we need to set spiclk on slave side also ,as it shud take
that as input frm master only ?
also do reply if  there is anyother point that i m not taking into
consideration
i wud also appreciate directC source code for spi configuration of
lpc936.

On 6 Sep 2006 21:08:12 -0700, "abhay" <abhaym244@gmail.com> wrote:

>hi all,
>i m interfacing my philips micro sdk lpc936(slave) wid philips arm
>micro sdk lpc2138(master).i m sending seven segment pattern thru master
>.the slave pin SS is connected to one port pin of master thet provides
>it logic high to select  it as slave.
>do need to check the status of SS pin on slave side periodically
>between byte transfers?

No.  Why would you need to check it between byte transfers?  Why would
you need to check it at all?  It's SPIF that you want to check, which
indicates that the master has asserted SS, clocked in a byte, and
negated SS.  That's all you need to check.

>i m doing this wid polling on master side & interrupt driven on slave
>side.
>
>i hav configured master spiclk as cclk/31 (58.5895/31.33 = 1.843MHz) &
>of slave as cclk/4 (7.373/4 =  1.843MHz) .do i need to consider
>anything else for spiclk.
>
>however do we need to set spiclk on slave side also ,as it shud take
>that as input frm master only ?

A slave is clocked by the master.

>also do reply if  there is anyother point that i m not taking into
>consideration
>i wud also appreciate directC source code for spi configuration of
>lpc936.
-- 
Dan Henry

Dan Henry wrote:
> On 6 Sep 2006 21:08:12 -0700, "abhay" <abhaym244@gmail.com> wrote:
>
> >hi all,
> >i m interfacing my philips micro sdk lpc936(slave) wid philips arm
> >micro sdk lpc2138(master).i m sending seven segment pattern thru master
> >.the slave pin SS is connected to one port pin of master thet provides
> >it logic high to select  it as slave.
> >do need to check the status of SS pin on slave side periodically
> >between byte transfers?
>
> No.  Why would you need to check it between byte transfers?  Why would
> you need to check it at all?  It's SPIF that you want to check, which
> indicates that the master has asserted SS, clocked in a byte, and
> negated SS.  That's all you need to check.
>
> >i m doing this wid polling on master side & interrupt driven on slave
> >side.
> >
> >i hav configured master spiclk as cclk/31 (58.5895/31.33 = 1.843MHz) &
> >of slave as cclk/4 (7.373/4 =  1.843MHz) .do i need to consider
> >anything else for spiclk.
> >
> >however do we need to set spiclk on slave side also ,as it shud take
> >that as input frm master only ?
>
> A slave is clocked by the master.
>
but do we need to consider the clk limits for slave.coz the slave clks
are not in exact multiples of spiclk from master.also how wud the
interrupt be generated & how we gonna detect it.do u have some code
regarding my problem?i wud be thankful to you in that case.

"abhay" <abhaym244@gmail.com> wrote in message
news:1157699797.437978.182110@p79g2000cwp.googlegroups.com...
> but do we need to consider the clk limits for slave.
Only the hardware limits of the slave device like max clock frequency.

> coz the slave clks
> are not in exact multiples of spiclk from master.

That's got nothing to do with it. There is no such thing as a slave clock
generator. The slave is clocked by the CLK of the SPI bus.

> also how wud the
> interrupt be generated & how we gonna detect it.

The interrupt is generated after 8 clock pulses from the master, when SS is
asserted.

Meindert

I'm also facing the similar problem while interfacing the two micros
where one is running at 50 MHz as master and the other at 10 MHz as
slave. The limit mentioned for the SPI clock is 4.5MHz.  I have clocked
it at 2.5MHz and also at 1Mhz. There is no interrupt getting generated
also the data is not transferred even in the polled way. What shall we
keep in mind for having SPI for the commnication between these micros
and I have to use mutiple of slave micros for one of my projects.