AT91RM9200 it's easy to broke data lines ?

Hi,
I'm going to run my board with AT91RM9200. My board has 32bit SDRAM (2 x 
HY57V561620C) data bus width. I saw that some data lines was tied together 
D24 D25 and D26 (close to CPU). I reworked them - now looks clear (I checked 
contacts too) but my memory test shows that lines D24 and D25 are still 
high. So my question is - Is it Atmel so fragile ? Could I broke it ?

Here is part of my SDRAM initialisation. Maybe should I do something more ?

/*
    AT91F_PIO_CfgPeriph(
     AT91C_BASE_PIOC, // PIO controller base address
         0xFFFF0030,
                 0
                        );
*/
  outl(0xFFFFF804, 0xFFFFFFFF); //AT91F_PIO_CfgPeriph
  for(i = 0; i < 100; i++);
  outl(EBI_CSA, 0x2);
  for(i = 0; i < 100; i++);
  outl(SDRAMC_CR, 0x2188A159); //takie wyliczylem
  for(i = 0; i < 100; i++);
  outl(SDRAMC_MR, 0x02); //All banks precharge and 32bits
  outl(AT91_SDRAM_BASE, 0);
  outl(SDRAMC_MR, 0x04); //Refresh and 32 bits
  outl(AT91_SDRAM_BASE, 0);
  outl(AT91_SDRAM_BASE, 0);
  outl(AT91_SDRAM_BASE, 0);
  outl(AT91_SDRAM_BASE, 0);
  outl(AT91_SDRAM_BASE, 0);
  outl(AT91_SDRAM_BASE, 0);
  outl(AT91_SDRAM_BASE, 0);
  outl(AT91_SDRAM_BASE, 0);
  outl(SDRAMC_MR, 0x03);  //Load Mode Register and 32bits
  for(i = 0; i < 100; i++);
  outl(0x20000080, 0);
  outl(SDRAMC_TR, 0x1C0);
  outl(AT91_SDRAM_BASE, 0);
  outl(SDRAMC_MR, 0x00);  //Normal Mode and 32bits


Best regards
Pelos