High Vin LDO with truely low dropout in small package (long post)

On 7 Oct 2006 14:15:11 -0700, "rickman" <gnuarm@gmail.com> wrote:

>John Larkin wrote:
>> A simple homemade hysteretic switcher should be efficient down to
>> roughly zero current, if you allow a bit of ripple. As far as syncing
>> with a clock to reduce EMI, well, I don't understand that... isn't it
>> better to spread out the spectral lines instead of heaping them all on
>> top one another?
>
>Two problems with that idea.  First spreading the spectrum may or may
>not reduce the problem.  For example, using a moving frequency for the
>clock may result in a test measurement that is lower, but does it
>really reduce the interference problem or does it just allow you to
>pass a test?

What matters, other than passing the test?


> The interfering spur is still the same amplitude, it is
>just moving while you test and so is integrated over a wider frequency
>range giving an average lower reading.
>

Exactly. But I wasn't suggesting deliberate dithering or anything,
just wondering what advantage there might be from syncing the switcher
to the system clock.

>Secondly, in the case of power supplies, you will be generating spurs
>either way, sync'd or not sync'd.  But if you sync all the supplies to
>the same clock, at least they are all creating the same harmonics.
>There are other ways to deal with the spurs since you can't get rid of
>them.
>
>If it is easy to make a switcher with good efficiency at low currents,
>why aren't there chips available to do that? 

Dunno. I did say "homemade."

John

rickman wrote:
> We often need to power low current circuits (<100 mA) from a wide
> battery voltage of 7 to 16.5 volts.  It is hard to find switching
> regulators that will do this efficiently.
(snip)
Have you looked at National's LM2736 to do the whole job?

Efficiency at 3.3 V and 100 mA out is 70% with 18 volts in 
and 34% at 10 mA out.  With a 5 volt supply those two 
efficiencies rise to 86% and 62%.
http://cache.national.com/ds/LM/LM2736.pdf

The slightly simpler LM2674
http://cache.national.com/ds/LM/LM2674.pdf
wastes about 3 mA plus switching losses, and might also work 
for you.

John Popelish wrote:
> rickman wrote:
> 
>> We often need to power low current circuits (<100 mA) from a wide
>> battery voltage of 7 to 16.5 volts.  It is hard to find switching
>> regulators that will do this efficiently.

This one (LT3470) has even better efficiency at low current 
and a low parts count:
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1003,C1042,P8810,D6297

Output at 3.3 volts:

With 7 volts in and 1 mA out, 74%.
With 7 volts in and 100 Ma out. 80%.

With 24 volts in and 1 mA out, 64%.
With 24 volts in and 100 mA out, 72%.

rickman wrote:
> We often need to power low current circuits (<100 mA) from a wide
> battery voltage of 7 to 16.5 volts.  It is hard to find switching
> regulators that will do this efficiently.  Sometimes we can just write
> off the wasted power and use an LDO if the current is low enough, but I
> am looking to find a way to reclaim this lost efficiency.
>
> I am thinking of building a switched capacitor voltage converter that
> can lower the input voltage over this input voltage range to something
> that is suitable for an LDO.  The circuit would use a CPLD (powered by
> this circuit) to generate the control signals for a small army of P and
> N channel FETs (or possibly analog switches) to control three flying
> capacitors.  I have done a lot of searching and found a 2 x 3 mm
> complementary FET that has the required characteristics that should
> work well.  I have also found a 4 channel comparator with a built in
> reference.  Now I only have two remaining problems.
>
> The first is figuring out how to start up the circuit.  I have come up
> with a couple of ideas that will bypass the switches until the output
> voltage is up to snuff and the CPLD starts running the switches.
> However this is hard to do without exposing the LDO following the
> switched cap converter to the full Vin of 16.5 volts.
>
> This is the second problem.  If I try to find an LDO with Vin up to
> 16.5 volts, output current up to 100 mA and dropout voltage of 200 mV,
> I come up short.  Considering some losses in the switching circuit,
> even to work with a dropout of 200 mV will realistically require the
> output voltage to be lower than the 3.3 volts I would like to use.  But
> I can likely live with 3.2 or even 3.1 volts if the accuracy on the LDO
> is good enough to keep it above 3.0 volts worst case.
>
> I can't raise the 7 volt Vin minimum requirement, so I am stuck with a
> 200 mV dropout.  I can get this in a low Vin device, but not a high Vin
> device in a small package.  So far I have tried to keep this as simple
> as possible and not used anything like a "pre-regulator" or Zener
> diode.  But I'm not happy with my choices.
>
> Anyone have any suggestions on a better way to improve this circuit?

I'm missing something here. The minimum input voltage is 7V. The output
is 3.3V. Just how does this work out to a drop out voltage of 200mV?
Can't you buck the input down to 4.3V, and use just about any LDO.

Having designed a few SMPS, there are plenty of gotchas. You are always
better off buying an IC controller. There is much black magic in
controller chips that the user never sees, mostly related to
undervoltage lock-out and start-up situations.

John Popelish wrote:
> John Popelish wrote:
> > rickman wrote:
> >
> >> We often need to power low current circuits (<100 mA) from a wide
> >> battery voltage of 7 to 16.5 volts.  It is hard to find switching
> >> regulators that will do this efficiently.
>
> This one (LT3470) has even better efficiency at low current
> and a low parts count:
> http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1003,C1042,P8810,D6297
>
> Output at 3.3 volts:
>
> With 7 volts in and 1 mA out, 74%.
> With 7 volts in and 100 Ma out. 80%.
>
> With 24 volts in and 1 mA out, 64%.
> With 24 volts in and 100 mA out, 72%.

Thanks for the tips, but I have looked at all of these devices as well
as many more.  This is the third time I have done this same power
supply search for these parameters.  If there was an inductive switcher
out there that did a good job at 10 mA of current, I would have found
it.  But the combination of low current and high Vin seems to be
deadly.  In addition, all but a few of the high Vin regulators are
non-synchrnous and many of those also require a boost diode.  By the
time you add the sizes of all these components you are using a fair
hunk of real estate and not getting much in the way of efficiency.

Designing an inductive switcher may well be complex.  But a multimode
switched capacitor circuit is mostly a digital design along with
careful control of the detailed timing.  The only timing issue I am
concerned about is that the P channel FETs must be driven through N
channel FETs.  These devices add much more delay to the path than the
logic circuits will.  To make sure there is no shoot through I will
have to compensate these delays compared to the N channel FETs used on
the low side of the caps.  I may have to add N channel FETs to drive
the N channel FETs just to equalize the delays.

But what I asked for help on was selecting an LDO that meets my
requirements.

miso@sushi.com wrote:
> I'm missing something here. The minimum input voltage is 7V. The output
> is 3.3V. Just how does this work out to a drop out voltage of 200mV?
> Can't you buck the input down to 4.3V, and use just about any LDO.
>
> Having designed a few SMPS, there are plenty of gotchas. You are always
> better off buying an IC controller. There is much black magic in
> controller chips that the user never sees, mostly related to
> undervoltage lock-out and start-up situations.

Yes, you missed that I am using a switched cap voltage divider in front
of the LDO.  Inductive switchers are too inefficient.  Between input
voltages of 7 to 10.5 I expect to use a 2:1 divider and higher ratios
at higher voltages.  This gives me 3.5 volts to the LDO if the switcher
is optimal.    I expect the switcher drop out to be minimal as the FETs
I am using are sub ohm resistance.  I found nice small complementary
FETs in a 2x3 mm package rated for healthy currents and low voltage
drive.  So assuming I loose 100 mV in the switcher and 200 mV in the
LDO, I can still get 3.2 volts out of the LDO.  If the tolerance
(including set resistors) is +-3%, I can set it for 3.1 volts and it
will not be below 3.0 volts or above 3.2 volts meeting all the limits.


I do have some concerns about the losses in the switcher.  But if they
are too high to run the switcher and LDO from 7 volts, I can always add
a 1:1 mode for the low end of the input voltage.

rickman wrote:

>
> I do have some concerns about the losses in the switcher.  But if they
> are too high to run the switcher and LDO from 7 volts, I can always add
> a 1:1 mode for the low end of the input voltage.

Just out of curiosity - what frequency will the switcher run?

Regards
Rocky

rickman wrote:

> We often need to power low current circuits (<100 mA) from a wide
> battery voltage of 7 to 16.5 volts.  It is hard to find switching
> regulators that will do this efficiently.  Sometimes we can just write
> off the wasted power and use an LDO if the current is low enough, but I
> am looking to find a way to reclaim this lost efficiency.
> 
> I am thinking of building a switched capacitor voltage converter that
> can lower the input voltage over this input voltage range to something
> that is suitable for an LDO.  The circuit would use a CPLD (powered by
> this circuit) to generate the control signals for a small army of P and
> N channel FETs (or possibly analog switches) to control three flying
> capacitors.  I have done a lot of searching and found a 2 x 3 mm
> complementary FET that has the required characteristics that should
> work well.  I have also found a 4 channel comparator with a built in
> reference.  Now I only have two remaining problems.
> 
> The first is figuring out how to start up the circuit.  I have come up
> with a couple of ideas that will bypass the switches until the output
> voltage is up to snuff and the CPLD starts running the switches.
> However this is hard to do without exposing the LDO following the
> switched cap converter to the full Vin of 16.5 volts.
> 
> This is the second problem.  If I try to find an LDO with Vin up to
> 16.5 volts, output current up to 100 mA and dropout voltage of 200 mV,
> I come up short.  Considering some losses in the switching circuit,
> even to work with a dropout of 200 mV will realistically require the
> output voltage to be lower than the 3.3 volts I would like to use.  But
> I can likely live with 3.2 or even 3.1 volts if the accuracy on the LDO
> is good enough to keep it above 3.0 volts worst case.
> 
> I can't raise the 7 volt Vin minimum requirement, so I am stuck with a
> 200 mV dropout.  I can get this in a low Vin device, but not a high Vin
> device in a small package.  So far I have tried to keep this as simple
> as possible and not used anything like a "pre-regulator" or Zener
> diode.  But I'm not happy with my choices.
> 
> Anyone have any suggestions on a better way to improve this circuit?

The LP2951/LP2954 family get close. Micrel & Advanced Monolithic do 
'better' versions of these, with -20/+60V ip.

You could also look at placing the LDO _before_ the switch-cap, since 
you say that has low Rs. That halves the LDO current, and also makes the
dropout a smaller % of higher voltage.

Also, because you DO have a higher voltage, that opens up boosted gate 
drive schemes, most often found in higher current regulators.

Have you looked at LED drive Switch modes ? - these are getting smarter
all the time, and often have mode changes, and are designed to deliver 
low load currents, at high efficencies - because they target handheld apps.

-jg

rickman wrote:
> John Larkin wrote:
> 
>>A simple homemade hysteretic switcher should be efficient down to
>>roughly zero current, if you allow a bit of ripple. As far as syncing
>>with a clock to reduce EMI, well, I don't understand that... isn't it
>>better to spread out the spectral lines instead of heaping them all on
>>top one another?
> 
> 
> Two problems with that idea.  First spreading the spectrum may or may
> not reduce the problem.  For example, using a moving frequency for the
> clock may result in a test measurement that is lower, but does it
> really reduce the interference problem or does it just allow you to
> pass a test?   The interfering spur is still the same amplitude, it is
> just moving while you test and so is integrated over a wider frequency
> range giving an average lower reading.
> 
> Secondly, in the case of power supplies, you will be generating spurs
> either way, sync'd or not sync'd.  But if you sync all the supplies to
> the same clock, at least they are all creating the same harmonics.
> There are other ways to deal with the spurs since you can't get rid of
> them.
> 
> If it is easy to make a switcher with good efficiency at low currents,
> why aren't there chips available to do that?  We get a fair amount of
> attention from the vendors because we sell a lot of units.  They all
> try to sell me the same 1.5 Amp high Vin switchers with low efficiency
> at low currents.  The TI part is the best one I have seen so far and it
> is terrible below about 30 mA.
> 

A switcher in burst mode has less transients than in
PWM mode. Thus generates less EMI. If you want low
EMI, then you have to choose a switcher with
controlled/slower transients.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

On 7 Oct 2006 12:27:36 -0700, "rickman" <gnuarm@gmail.com> wrote:

>John Larkin wrote:
>> Revisit the idea of using a buck switcher? That doesn't seem difficult
>> over a mere 2:1 or so input range, and it will be a lot simpler than a
>> switch+cap array, control logic, and an LDO.
>
>Yes, simple, but very inefficient.  At 100 mA it may not be so bad at
>around 50-60% typically, but at 10 mA or lower the efficiency goes to
>heck in a handbasket.  

If you're worried about 10mA why on earth are you considering using a CPLD for anything...?