is systemC capable of generating synthesizable hardware descriptions from a c code. if so, how does it compare with impulse C interms of features? thanks
what is system C.
Started by ●October 21, 2006
Reply by ●October 22, 20062006-10-22
SystemC is a concurrent (parallel) language similar to languages like VHDL and Verilog whereas C is an untimed sequential language. SystemC doesn't "generate" synthesisable descriptions, for that you need a SystemC synthesis tool like Celoxica's Agility. If you are thinking of using an FPGA I would suggest you also look at VHDL/Verilog which might be easier in terms of tools support, free IP cores and capabilities. I am not against C for hardware design (I think it's the way forward) but I don't believe it is mature enough unless you can afford tools like Mentors's Catapult or Forte's Cynthesiser :-) Hans www.ht-lab.com <manusha@millenniumit.com> wrote in message news:1161456373.506323.238130@h48g2000cwc.googlegroups.com...> is systemC capable of generating synthesizable hardware descriptions > from a c code. if so, how does it compare with impulse C interms of > features? > > thanks >
Reply by ●October 23, 20062006-10-23
> I am not against C for hardware design (I think it's the > way forward)Nah, the future's BerryHDL. ;-) An example: module UartTX(BITS = 8) { inport clk, rst, data[BITS - 1:0], wr, bitClock; outport tx, ready; reg sr[BITS + 4:0]; sr.clk = clk; tx = sr[0]; ready = 1 when sr == 1; sr = { all: 1 when rst; 1, 1, data[BITS - 1] ^ .. data[0], data[BITS - 1:0], 0, 1 when wr; 0, sr[BITS + 4:1] when bitClock & (sr != 1); } }
Reply by ●October 23, 20062006-10-23
What is BerryHDL ? I found nothing in google... -daniel Paul Taylor wrote:> > I am not against C for hardware design (I think it's the > > way forward) > > Nah, the future's BerryHDL. > ;-) > > An example: > > module UartTX(BITS = 8) { > inport clk, rst, data[BITS - 1:0], wr, bitClock; > outport tx, ready; > reg sr[BITS + 4:0]; > sr.clk = clk; > tx = sr[0]; > ready = 1 when sr == 1; > sr = { > all: > 1 when rst; > 1, 1, data[BITS - 1] ^ .. data[0], data[BITS - 1:0], 0, 1 when wr; > 0, sr[BITS + 4:1] when bitClock & (sr != 1); > } > }
Reply by ●October 24, 20062006-10-24
On Mon, 23 Oct 2006 16:54:39 -0700, kunil wrote:> What is BerryHDL ? I found nothing in google... > -daniel >It's my pet project. I expect to release source code early next year. http://myweb.tiscali.co.uk/pault/ The line about the future being BerryHDL was very much tongue in cheek.
Reply by ●October 24, 20062006-10-24
Hi Paul, I hope you are doing this as a research/PhD project and not trying to make a living out of it :-) Hans www.ht-lab.com "Paul Taylor" <paul_ng_pls_rem@tiscali.co.uk> wrote in message news:pan.2006.10.24.08.09.39.311825@tiscali.co.uk...> On Mon, 23 Oct 2006 16:54:39 -0700, kunil wrote: > >> What is BerryHDL ? I found nothing in google... >> -daniel >> > > It's my pet project. I expect to release source code early next year. > > http://myweb.tiscali.co.uk/pault/ > > The line about the future being BerryHDL was very much tongue in cheek. > > >
Reply by ●October 25, 20062006-10-25
On Tue, 24 Oct 2006 19:59:30 +0000, Hans wrote:> I hope you are doing this as a research/PhD project and not trying to make a > living out of it :-)You liked it that much then :-) No, it's not something I plan to make a living from. It's more or less a toy. Something I play with on dark British winter nights (on the nights when when I'm not entertaining my wife, which is much more fun). As you liked the uart transmitter example so much, I have included the receiver below. It's basically three state machines/sequential blocks. Regards, Paul. module UartRX(BITS = 8) { inport clk, rst, rx, bitClock16; outport data[BITS - 1:0], parityErr, framingErr, dataRdy; node rstRxDivider, rstRxReg, sample; reg sr[BITS + 2:0], sampleCount[3:0], sm[1:0]; sr.clk = sampleCount.clk = sm.clk = clk; data = sr[BITS:1]; parityErr = sr[BITS + 1] ^ .. sr[1]; framingError = !sr[BITS + 2]; sr = { all: dataRdy = 1 when sr[0] == 0; all 1 when rst | rstRxReg; rx, sr[bits + 4:1] when sample; } sampleCount = { all: 0 when rst | rstRxDivider; next when bitClock16; 7: sample = 1; } sm = { all: 0 when rst; 0: rstRxDivider = 1 next when !rx with rstRxReg = 1; 1: 0 when rx & sample with rstRxDivider = 1; next when !rx & sample; 2: 0 when dataRdy; } }
Reply by ●October 25, 20062006-10-25
Hi Paul, I also have to enjoy those British winter nights :-( It looks like an interesting project which will certainly consume a lot of these nights :-) Good luck with the project, Hans www.ht-lab.com "Paul Taylor" <paul_ng_pls_rem@tiscali.co.uk> wrote in message news:pan.2006.10.25.07.49.34.776090@tiscali.co.uk...> On Tue, 24 Oct 2006 19:59:30 +0000, Hans wrote: > > >> I hope you are doing this as a research/PhD project and not trying to >> make a >> living out of it :-) > > You liked it that much then :-) > > No, it's not something I plan to make a living from. It's more or less a > toy. Something I play with on dark British winter nights (on > the nights when when I'm not entertaining my wife, which is much more > fun). > > As you liked the uart transmitter example so much, I have included the > receiver below. It's basically three state machines/sequential blocks. > > Regards, > > Paul. > > module UartRX(BITS = 8) { > inport clk, rst, rx, bitClock16; > outport data[BITS - 1:0], parityErr, framingErr, dataRdy; > node rstRxDivider, rstRxReg, sample; > reg sr[BITS + 2:0], sampleCount[3:0], sm[1:0]; > sr.clk = sampleCount.clk = sm.clk = clk; > > data = sr[BITS:1]; > parityErr = sr[BITS + 1] ^ .. sr[1]; > framingError = !sr[BITS + 2]; > > sr = { > all: > dataRdy = 1 when sr[0] == 0; > all 1 when rst | rstRxReg; > rx, sr[bits + 4:1] when sample; > } > > sampleCount = { > all: > 0 when rst | rstRxDivider; > next when bitClock16; > 7: > sample = 1; > } > > sm = { > all: > 0 when rst; > 0: > rstRxDivider = 1 > next when !rx with rstRxReg = 1; > 1: > 0 when rx & sample with rstRxDivider = 1; > next when !rx & sample; > 2: > 0 when dataRdy; > } > } >
