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Memory Mapped Vs I/O Mapped Vs others

Started by karthikbg December 17, 2006
Hi,

Thx for all of your replies that gave me clarifications.

Got some good info from the net regarding this -  i have placed it
below ....

Generally, Processor families have two distinct address spaces
through which they can communicate with these memories and peripherals.
The first address space is called the memory space and is intended
mainly for memory devices; the second is reserved exclusively for
peripherals and is called the I/O space. However, peripherals can also
be located within the memory space, at the discretion of the hardware
designer. When that happens, we say that those peripherals are
memory-mapped.

>From the processor's point of view, memory-mapped peripherals look and
act very much like memory devices. However, the function of a peripheral is obviously quite different from that of a memory. Instead of simply storing the data that is provided to it, a peripheral might instead interpret it as a command or as data to be processed in some way. If peripherals are located within the memory space, we say that the system has memory-mapped I/O. The designers of embedded hardware often prefer to use memory-mapped I/O exclusively, because it has advantages for both the hardware and software developers. It is attractive to the hardware developer because he might be able to eliminate the I/O space, and some of its associated wires, altogether. This might not significantly reduce the production cost of theboard, but it might reduce the complexity of the hardware design. Memory-mapped peripherals are also better for the programmer, who is able to use pointers, data structures, and unions to interact with the peripherals more easily and efficiently. Chips are located in the processor's memory space, and the processor communicates with them by way of two sets of electrical wires called the address bus and the data bus. To read or write a particular location in memory, the processor first writes the desired address onto the address bus. The data is then transferred over the data bus. The memory map contains one entry for each of the memories and peripherals that are accessible from the processor's memory space. Mostly External RAM,ROM,FLASH memory devices come in this region. If a separate I/O space is present, and devices are connected at that region, then it is called as I/O Mapped. Typically, a large percentage of the I/O space will be unused because most of the peripherals located there will have only a handful of registers. Devices like the peripheral control block (PCB), parallel port, and debugger port etc.... come in this region. Unfortunately, registers within the I/O space of an 80x86 processor can be accessed only by using the assembly language instructions in and out. The C language has no built-in support for these operations. The actual algorithm is straightforward: read the contents of the register, toggle the bit that controls the I/O (LED etc) of interest, and write the new value back into the register. You will notice that although this routine is written in C, the functional part is actually implemented in assembly language. This is a handy technique, known as inline assembly. Regards, Karthik Balaguru
Himanshu Chauhan <hs.chauhan@gmail.com> wrote:
> Pete Fenelon wrote: >> Crikey, is that book still going? It was the freshman digital >> electronics text I used over 20 years ago ;P > > But you still started with that book, right? And now your experience > builds on that book, ain't it? >
No, I found that the course notes were infinitely better than the book, and that Horowitz & Hill was better still. Mano is not a book I remember fondly, in fact it was one of the texts I sold off immediately I'd finished using it! pete -- pete@fenelon.com "he just stuck to buying beer and pointing at other stuff"
On 2006-12-21, karthikbg <karthik.balaguru@lntinfotech.com> wrote:

> Got some good info from the net regarding this - i have placed it > below .... > > Generally, Processor families have two distinct address spaces > through which they can communicate with these memories and peripherals.
No, that's not "generally" true. _Some_ processors have two distinct address spaces. Some only have one. Some have three or more.
> The first address space is called the memory space and is > intended mainly for memory devices; the second is reserved > exclusively for peripherals and is called the I/O space.
Sort of. You can put memory in I/O space if you want. The difference between the two address spaces is which instructions are used to access them. Also, some processors have multiple memory address spaces. The most common implementation of that uses one memory address space for instructions (code), and a separate one for data. That's called a Harvard architecture. Some Harvard architecture processors have a third address space for I/O peripherals.
> However, peripherals can also be located within the memory > space, at the discretion of the hardware designer. When that > happens, we say that those peripherals are memory-mapped.
Yes. [...]
> Memory-mapped peripherals are also better for the programmer, > who is able to use pointers, data structures, and unions to > interact with the peripherals more easily and efficiently.
Yes, although there are numerous pitfalls when using memory-mapped I/O devices in the manners mentioned. -- Grant Edwards grante Yow! Actually, what at I'd like is a little toy visi.com spaceship!!
"karthikbg" <karthik.balaguru@lntinfotech.com> writes:
> > Thx for all of your replies that gave me clarifications. > > Got some good info from the net regarding this - i have placed it > below .... > > Generally, Processor families have two distinct address spaces > through which they can communicate with these memories and peripherals.
I would take exception with the use of "generally". I/O-mapping seems to have been initiated by Intel way back when and only the look-alikes (Zilog, et al) ever followed that lead.
Everett M. Greene wrote:

> "karthikbg" <karthik.balaguru@lntinfotech.com> writes: > > > > Thx for all of your replies that gave me clarifications. > > > > Got some good info from the net regarding this - i have placed it > > below .... > > > > Generally, Processor families have two distinct address spaces > > through which they can communicate with these memories and peripherals. > > I would take exception with the use of "generally". > I/O-mapping seems to have been initiated by Intel > way back when and only the look-alikes (Zilog, et > al) ever followed that lead.
True, the texas 9900 series and transputers had their I/O on serial links, not mapped anywhere.
cbarn24050@aol.com wrote:

> Everett M. Greene wrote: > > >>"karthikbg" <karthik.balaguru@lntinfotech.com> writes: >> >>>Thx for all of your replies that gave me clarifications. >>> >>>Got some good info from the net regarding this - i have placed it >>>below .... >>> >>>Generally, Processor families have two distinct address spaces >>>through which they can communicate with these memories and peripherals. >> >>I would take exception with the use of "generally". >>I/O-mapping seems to have been initiated by Intel >>way back when and only the look-alikes (Zilog, et >>al) ever followed that lead. > > > True, the texas 9900 series and transputers had their I/O on serial > links, not mapped anywhere.
Yeah but... DEC's PDP 8 used I/O ports for I/O and the PDP 11 used memory-mapped I/O long before Intel or Mot fabbed a single processor wafer.
Everett M. Greene wrote:
> "karthikbg" <karthik.balaguru@lntinfotech.com> writes: > >>Thx for all of your replies that gave me clarifications. >> >>Got some good info from the net regarding this - i have placed it >>below .... >> >>Generally, Processor families have two distinct address spaces >>through which they can communicate with these memories and peripherals. > > > I would take exception with the use of "generally". > I/O-mapping seems to have been initiated by Intel > way back when and only the look-alikes (Zilog, et > al) ever followed that lead.
That is actually far older - predating all microprocessors. On the first mini's, the Digital PDP-8 used separate I/O instructions (and I/O mapping), but PDP-11 used memory mapping. In the minicomputer time, separate I/O was more often used, so the memory-mapped PDP-11 was kind of a weird bird. -- Tauno Voipio tauno voipio (at) iki fi
"Everett M. Greene" wrote:
> "karthikbg" <karthik.balaguru@lntinfotech.com> writes: > >> Thx for all of your replies that gave me clarifications. >> >> Got some good info from the net regarding this - i have placed >> it below .... >> >> Generally, Processor families have two distinct address spaces >> through which they can communicate with these memories and >> peripherals. > > I would take exception with the use of "generally". I/O-mapping > seems to have been initiated by Intel way back when and only the > look-alikes (Zilog, et al) ever followed that lead.
In 1969 or earlier the Microdata machine used separate i/o space, among small machines. Big iron, such as the IBM 360, actually used a separate i/o processor and separate space, known as i/o channels. I'm sure there are many more early examples. IIRC the SDS machines of 1963 or so are included (which later became Xerox machines). I never used it, but my bus system and cpu cards for the 8080 (1973/4) had provision for remapping a block of memory space into i/o space. This was meant to "simplify?" code, without altering the peripheral hardware. IIRC it was enabled by a dipswitch jumper on the CPU card. I consider memory mapping peripherals dangerous. It effectively prevents scanning memory for actually installed memory, because arbitrary writes (or even reads) to/from i/o devices can do evil things. It also makes it possible for wild pointers to destroy the external storage, or worse. Cross-posted to alt.folklore.computers, where the other old fogies tend to hang out. They will probably correct me and expand on my blathering. -- Chuck F (cbfalconer at maineline dot net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net>
CBFalconer wrote:
> "Everett M. Greene" wrote: > > "karthikbg" <karthik.balaguru@lntinfotech.com> writes: > > > >> Thx for all of your replies that gave me clarifications. > >> > >> Got some good info from the net regarding this - i have placed > >> it below .... > >> > >> Generally, Processor families have two distinct address spaces > >> through which they can communicate with these memories and > >> peripherals. > > > > I would take exception with the use of "generally". I/O-mapping > > seems to have been initiated by Intel way back when and only the > > look-alikes (Zilog, et al) ever followed that lead. > > In 1969 or earlier the Microdata machine used separate i/o space, > among small machines. Big iron, such as the IBM 360, actually used > a separate i/o processor and separate space, known as i/o > channels. I'm sure there are many more early examples. IIRC the > SDS machines of 1963 or so are included (which later became Xerox > machines). > > I never used it, but my bus system and cpu cards for the 8080 > (1973/4) had provision for remapping a block of memory space into > i/o space. This was meant to "simplify?" code, without altering > the peripheral hardware. IIRC it was enabled by a dipswitch jumper > on the CPU card. > > I consider memory mapping peripherals dangerous. It effectively > prevents scanning memory for actually installed memory, because > arbitrary writes (or even reads) to/from i/o devices can do evil > things. It also makes it possible for wild pointers to destroy the > external storage, or worse. > > Cross-posted to alt.folklore.computers, where the other old fogies > tend to hang out. They will probably correct me and expand on my > blathering. > > -- > Chuck F (cbfalconer at maineline dot net) > Available for consulting/temporary embedded and systems. > <http://cbfalconer.home.att.net>
Actually, Cross-posted from : http://groups.google.co.in/group/comp.arch.embedded/browse_frm/thread/8999bc6e4e509ec7?hl=en Regards, Karthik Balaguru
karthikbg wrote:
> CBFalconer wrote: >
... snip ...
>> >> Cross-posted to alt.folklore.computers, where the other old fogies >> tend to hang out. They will probably correct me and expand on my >> blathering. > > Actually, Cross-posted from : > http://groups.google.co.in/group/comp.arch.embedded/browse_frm/thread/8999bc6e4e509ec7?hl=en
No, my original is correct. Google is just a poor interface to the actual Usenet system. -- Chuck F (cbfalconer at maineline dot net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net>