test UART

Hi, All

I want to use UART to do the transmission between Matlab and FPGA
board. I found one from others. I made a simple test to realize
transmit data to uart and transmit back to matlab. I will write some
parts codes of my test here to make sure you know what I am doing.

entity uart-top is
	port(
		sys_clock : in std_logic;
		PB_LEFT   : in std_logic;
		RS232_RTS_IN : IN std_logic;
		RS232_RX_DATA : IN std_logic;
		RS232_CTS_OUT : OUT std_logic;
		RS232_TX_DATA : OUT std_logic
		);
end uart-top;
COMPONENT uart115200
	PORT(
		SYSCLK : IN std_logic;
		RS232_RTS_IN : IN std_logic;
		RS232_RX_DATA : IN std_logic;
		RESET : IN std_logic;
		READ : IN std_logic;
		WRITE : IN std_logic;
		DATAOUT : IN std_logic_vector(7 downto 0);
		RS232_CTS_OUT : OUT std_logic;
		RS232_TX_DATA : OUT std_logic;
		DATAIN : OUT std_logic_vector(7 downto 0);
		RXRDY : OUT std_logic;
		TXRDY : OUT std_logic;
		parityerr : OUT std_logic;
		framingerr : OUT std_logic
		);
END COMPONENT;

dataout <=3D datain;
write <=3D read;

test_inst: process(sysclk)
			  variable  rxrdy1 :=3D std_logic:=3D '0';
		 begin
		 		if reset =3D '1' then
					read  <=3D '0';
					txrdy1 :=3D '0';
				elsif sysclk'event and sysclk =3D'1' then
					if rxrdy1 =3D'0' and rxrdy =3D'1' then
					    read <=3D '1';
					end if;
					if rxrdy1 =3D'1' and rxrdy =3D'0' then
					    read <=3D '0';
					end if;
					rxrdy1 :=3D rxrdy;
				end if;
			end process;
It works well. Data  are transmitted from matlab to fpga, and send
back correctly.
---------------------------------------------------------------------------=
----------------------------

Next, I want to add an Array in this test

First=EF=BC=8CData are witten into uart and saved in a tempary Array. When =
the
counter=3DNumByteData, Data are sent back to Matlab.

I don't know how to control the write signal and read signal here.

I still use the change of 'rxrdy' to control the Read signal like I
use to do it. But this time I did not connect READ with WRITE. I want
to to use index of Array to trigger WRITE signal. So I do this

est_inst: process(wrramclk)
 variable  rxrdy1: std_logic:=3D'0';
		 begin
		 if reset =3D '1' then
		     readb  <=3D '0';
		     rxrdy1 :=3D '0';
		elsif wrramclk'event and wrramclk =3D'1' then
		    if rxrdy1 =3D'0' and rxrdy =3D'1' then
		        readb <=3D '1';
		    end if;
		 if rxrdy1 =3D'1' and rxrdy =3D'0' then
		        readb <=3D '0';
		end if;
		rxrdy1 :=3D rxrdy;
		end if;
end process;

countRX_inst:  process(WRRAMCLK,RESET)
VARIABLE CNT : STD_LOGIC_VECTOR (4 DOWNTO 0) :=3D(others=3D>'0');
VARIABLE rd1,rd2,rd3,rd4: std_logic:=3D'0';
VARIABLE TMP: STD_LOGIC :=3D'0
  begin
       if (RESET =3D '1') then
                   CNT :=3D (OTHERS =3D>'0');
                   index1 <=3D0;
                   rd1 :=3D '0';
                   rd2 :=3D '0';
                  rd3 :=3D '0'
elsif WRRAMCLK'event and WRRAMCLK =3D '1' then
                    if rd4 =3D '0' and rd3 =3D '1' and rd2 =3D '1' and rd1
=3D'1' then   --detect the rising edge of read
tmpH(index1)<=3Ddatain;   --read data from input-register in uart to
tempary_array input register										       CNT :=3D CNT +
"00001";								      index1 <=3D CONV_INTEGER(UNSIGNED(CNT));
writeb<=3D'0';									        IF index1=3D15 THEN
index1<=3D0; 								            writeb <=3D '1';
                       end if;
                  else   									          index1
<=3D0;									          CNT :=3D (OTHERS=3D> '0');
          end if;																				rd4 :=3D rd3;
                rd3 :=3D rd2;
                rd2 :=3D rd1;
                rd1 :=3D readb;   --delay "read"  three cycles
         end if;	;
	END PROCESS;
--------------------
I did not write out the whole codes. But these code above have already
shown what I am thinking.
It cannot work. Does anybody tell me what the problem of my design?
Thank you.

Zhi