Hi folks, I have a fairly simple synchronous logic circuit, using a handful of flipflops and gates, which ordinarily I'd breadboard using HC TTL. However, it needs an 80MHz clock, which is too high for such families. I suspect I might need to look at FPGAs, CPLDs etc, but it's been a long time since I looked at these, and my timescales are short. Could anyone suggest either a family or technology with a short learning curve, adequate speed, and reasonable costs? TIA, Steve http://www.fivetrees.com
80MHz clock, discrete logic
Started by ●February 20, 2007
Reply by ●February 20, 20072007-02-20
In comp.arch.embedded, Steve at fivetrees <steve@NOSPAMTAfivetrees.com> wrote:> Hi folks, > > I have a fairly simple synchronous logic circuit, using a handful of > flipflops and gates, which ordinarily I'd breadboard using HC TTL. However, > it needs an 80MHz clock, which is too high for such families. >The 74AHCT74 has a typical Fmax of 170MHz, 74F74 Fmax typ. 125MHz.> I suspect I might need to look at FPGAs, CPLDs etc, but it's been a long > time since I looked at these, and my timescales are short. Could anyone > suggest either a family or technology with a short learning curve, adequate > speed, and reasonable costs?Check the AHCT and F families, but there are also others. The logic section of the NXP website is a startingpoint. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)
Reply by ●February 20, 20072007-02-20
>... Could anyone > suggest either a family or technology with a short learning curve, adequate > speed, and reasonable costs?You will have little if any problems locating a family to do the job. Breadboarding at this speed is typically not practical, you are going to need power and ground planes. Dimiter On Feb 20, 2:09 pm, "Steve at fivetrees" <s...@NOSPAMTAfivetrees.com> wrote:> Hi folks, > > I have a fairly simple synchronous logic circuit, using a handful of > flipflops and gates, which ordinarily I'd breadboard using HC TTL. However, > it needs an 80MHz clock, which is too high for such families. > > I suspect I might need to look at FPGAs, CPLDs etc, but it's been a long > time since I looked at these, and my timescales are short. Could anyone > suggest either a family or technology with a short learning curve, adequate > speed, and reasonable costs? > > TIA, > > Stevehttp://www.fivetrees.com
Reply by ●February 20, 20072007-02-20
On Feb 20, 8:04 am, "Didi" <d...@tgi-sci.com> wrote:> >... Could anyone > > suggest either a family or technology with a short learning curve, adequate > > speed, and reasonable costs?You top posted and left out the important number: 80 MHz.> > You will have little if any problems locating a family to do the job. > Breadboarding at this speed is typically not practical, you are going > to need power and ground planes.More of a reason to use a single chip CPLD. Easy to find 200 to 300 MHz chips.
Reply by ●February 20, 20072007-02-20
"linnix" <me@linnix.info-for.us> wrote in message news:1171989074.900420.89950@v33g2000cwv.googlegroups.com...> On Feb 20, 8:04 am, "Didi" <d...@tgi-sci.com> wrote: >> >... Could anyone >> > suggest either a family or technology with a short learning curve, >> > adequate >> > speed, and reasonable costs? > > You top posted and left out the important number: 80 MHz. > >> >> You will have little if any problems locating a family to do the job. >> Breadboarding at this speed is typically not practical, you are going >> to need power and ground planes. > > More of a reason to use a single chip CPLD. > Easy to find 200 to 300 MHz chips.Thanks for the replies, chaps. Linnix: any particular CPLD family? I'm a CPLD virgin (although I have designed ASICs, about 20 years back...). Steve http://www.fivetrees.com
Reply by ●February 20, 20072007-02-20
"linnix" <me@linnix.info-for.us> wrote:> ... >More of a reason to use a single chip CPLD. >Easy to find 200 to 300 MHz chips. > >The original description of a "simple synchronous logic circuit, using a handful of flipflops and gates" does indeed suggest using a CPLD, but for the sake of completeness, it may be possible to simulate that logic in software. There are several small processors approaching or passing the 100 Mips mark. Roberto Waltman [ Please reply to the group, return address is invalid ]
Reply by ●February 20, 20072007-02-20
On Feb 20, 10:02 am, "Steve at fivetrees" <s...@NOSPAMTAfivetrees.com> wrote:> "linnix" <m...@linnix.info-for.us> wrote in message > > news:1171989074.900420.89950@v33g2000cwv.googlegroups.com... > > > On Feb 20, 8:04 am, "Didi" <d...@tgi-sci.com> wrote: > >> >... Could anyone > >> > suggest either a family or technology with a short learning curve, > >> > adequate > >> > speed, and reasonable costs? > > > You top posted and left out the important number: 80 MHz. > > >> You will have little if any problems locating a family to do the job. > >> Breadboarding at this speed is typically not practical, you are going > >> to need power and ground planes. > > > More of a reason to use a single chip CPLD. > > Easy to find 200 to 300 MHz chips. > > Thanks for the replies, chaps. > > Linnix: any particular CPLD family? I'm a CPLD virgin (although I have > designed ASICs, about 20 years back...). > > Stevehttp://www.fivetrees.comXilinx XC9536 should work.
Reply by ●February 20, 20072007-02-20
Steve at fivetrees wrote:> Linnix: any particular CPLD family? I'm a CPLD virgin (although I have > designed ASICs, about 20 years back...).What supply voltage(s) do you have ? Present fast/Low power CPLD Candiates are : Atmel ATF1502BE, in faster speed grade Tools: Suggest CUPL Boolean Design Entry, Similar to a C/ASM level of code. Lattice ispMach4000z family LC4032 Tools: Suggest ABEL Boolean Design Entry, Similar to a C/ASM level of code. Xilinx CoolrunnerII XC2C32A - Tools: Suggest ABEL Boolean Design Entry, Similar to a C/ASM level of code. All tools are free, but Xilinx and Lattice have larger downloads than Atmel, because they do not bother to do a separate CPLD tool flow, so you get boatloads of FPGA support along for the ride. All the above are ISP via JTAG First two families have dual supplies, and very low power (some uA levels). Lattice have that, and also do a variant with an on-chip regulator that bumps Icc to a few mA, but they lack Hystersis option. -jg
Reply by ●February 20, 20072007-02-20
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:45db4513$1@clear.net.nz...> Steve at fivetrees wrote: > >> Linnix: any particular CPLD family? I'm a CPLD virgin (although I have >> designed ASICs, about 20 years back...). > > What supply voltage(s) do you have ?The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL levels (i.e. 0-5V).> Present fast/Low power CPLD Candiates are :<snip> Superb. And thanks to linnix too. /me goes off to do some reading Steve http://www.fivetrees.com
Reply by ●February 20, 20072007-02-20
> You top posted and left out the important number: 80 MHz.I did not leave anything out. I just put it in the complete context I quoted at a place which apparently did not please you which is essentially your problem. I did post what I deemed relevant - the OP knew, as he had indicated, that CPLD was an obvious option. My suggestion may or may not have been obvious to him, it was informative in the context without restating what he obviously knew. But why bother about contents when we can concentrate on vital issues like top, bottom etc. posting religions. Dimiter On Feb 20, 6:31 pm, "linnix" <m...@linnix.info-for.us> wrote:> On Feb 20, 8:04 am, "Didi" <d...@tgi-sci.com> wrote: > > > >... Could anyone > > > suggest either a family or technology with a short learning curve, adequate > > > speed, and reasonable costs? > > You top posted and left out the important number: 80 MHz. > > > > > You will have little if any problems locating a family to do the job. > > Breadboarding at this speed is typically not practical, you are going > > to need power and ground planes. > > More of a reason to use a single chip CPLD. > Easy to find 200 to 300 MHz chips.
