what does a 'blank check' do exactly

on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding
information on this. Using Impact.

thanks!

<mtsukanov@gmail.com> wrote in message 
news:1172700224.105157.31840@s48g2000cws.googlegroups.com...
> on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding
> information on this. Using Impact.
>
> thanks!

A blank check gives me carte blanche?

Most programmable, non-volatile memories are one-way programmable; that is - 
when erased - all bits are one polarity and programming involved programming 
only the bits that are the opposite polarity.

This means that some meory can simply be "added to" but almost all of the 
time a new program involves changing some of the programmed polarities back 
to erased polarities.  Erasure can only occure on a block or device level 
for most of these devices.

The blank check tells you the reprogram *can* be successful because there 
are no unerased bits left that will need the erased status.  It's easier to 
check for the entire erasure than for just the bad bit polarities.

- John_H 

mtsukanov@gmail.com wrote:
> on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding
> information on this. Using Impact.

'blank check' means it checks the device is erased, ready to be programmed.

Normally used in a re-cycle situation, when you want to program
new code into the CPLD, you go along this chain of operations :

Erase/BlankCheck/Program/Verifty/Secure/VectorTest

Commonly devices are shipped blank, so the first 2 are optional
on a new device, but required on a already programmed device.

-jg

mtsukanov@gmail.com wrote:
> on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding
> information on this. Using Impact.

It reads back the program from the device and checks that the device is 
blank. That used to mean checking that all the bits were set to '1'. No 
doubt devices are more complicated now.

On Feb 28, 9:14 pm, Tim <t...@nooospam.roockyloogic.com> wrote:
> mtsuka...@gmail.com wrote:
> > on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding
> > information on this. Using Impact.
>
> It reads back the program from the device and checks that the device is
> blank. That used to mean checking that all the bits were set to '1'. No
> doubt devices are more complicated now.


I guess what I'm particularly asking is, on a 'blank check' do the
signals and/or pins in the CPLD get set to 0 or 1? or what?

I'm trying to find out because the particular design i'm working on,
'works' if I do a 'blank check' on the CPLD.

mtsukanov@gmail.com wrote:
> On Feb 28, 9:14 pm, Tim <t...@nooospam.roockyloogic.com> wrote:
>> mtsuka...@gmail.com wrote:
>>> on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding
>>> information on this. Using Impact.
>> It reads back the program from the device and checks that the device is
>> blank. That used to mean checking that all the bits were set to '1'. No
>> doubt devices are more complicated now.
> 
> 
> I guess what I'm particularly asking is, on a 'blank check' do the
> signals and/or pins in the CPLD get set to 0 or 1? or what?
> 
> I'm trying to find out because the particular design i'm working on,
> 'works' if I do a 'blank check' on the CPLD.

You should have the option to "erase part."  If you do that, then 
program the device without the "blank check" your design will still work.

If the check box is the difference between working and not working, then 
the software apparently notices the previously programmed device *isn't* 
blank and performs the erasure, setting all bits to the same polarity 
through the bulk erase process, allowing the programmed bits - and only 
the programmed bits - to be the opposite polarity.

If you're programming a bunch of new parts, it's convenient to skip the 
check for a blank device to save time.  If parts were never in the 
erased state, the device would always be erased first and there would be 
no need for that check box.

On Mar 1, 9:27 am, John_H <newsgr...@johnhandwork.com> wrote:
> mtsuka...@gmail.com wrote:
> > On Feb 28, 9:14 pm, Tim <t...@nooospam.roockyloogic.com> wrote:
> >> mtsuka...@gmail.com wrote:
> >>> on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding
> >>> information on this. Using Impact.
> >> It reads back the program from the device and checks that the device is
> >> blank. That used to mean checking that all the bits were set to '1'. No
> >> doubt devices are more complicated now.
>
> > I guess what I'm particularly asking is, on a 'blank check' do the
> > signals and/or pins in the CPLD get set to 0 or 1? or what?
>
> > I'm trying to find out because the particular design i'm working on,
> > 'works' if I do a 'blank check' on the CPLD.
>
> You should have the option to "erase part."  If you do that, then
> program the device without the "blank check" your design will still work.
>
> If the check box is the difference between working and not working, then
> the software apparently notices the previously programmed device *isn't*
> blank and performs the erasure, setting all bits to the same polarity
> through the bulk erase process, allowing the programmed bits - and only
> the programmed bits - to be the opposite polarity.
>
> If you're programming a bunch of new parts, it's convenient to skip the
> check for a blank device to save time.  If parts were never in the
> erased state, the device would always be erased first and there would be
> no need for that check box.


Hmm... I'm not completely sure I understand what u said, but let me
clarify a little more on what's happening:

The CPLD is connected to a xcf32 PROM and to a Xilinx V4 FPGA. All the
CPLD is doing is connecting the signals going from the PROM to the
FPGA - primarily the 'done' and 'd_in' pins. So, when I program the
CPLD, it works right away, and the FPGA gets programmed from the PROM.
If I turn off the POWER to the whole system, turn it back on - nothing
happens. The FPGA does'nt get programmed from the PROM. *IF at that
point I right click on the CPLD in Impact, and select 'blank check',
the CPLD starts 'working' and the FPGA gets programmed. The V4 is
working in 'master' mode, and I checked the CCLK and it runs just fine
after board powerup, thought the d_in has garbage on it. The d_in
turns good when i do the 'blank check' on the CPLD or when I reprogram
the CPLD. That's why I'm wondering if the 'blank check' drives the
CPLD's pins to 0 or 1 during the 'blank check' operation, something
funky like that

thanks again, any help is much appreciated

On Mar 1, 10:41 am, mtsuka...@gmail.com wrote:

> The CPLD is connected to a xcf32 PROM and to a Xilinx V4 FPGA. All the
> CPLD is doing is connecting the signals going from the PROM to the
> FPGA - primarily the 'done' and 'd_in' pins. So, when I program the
> CPLD, it works right away, and the FPGA gets programmed from the PROM.
> If I turn off the POWER to the whole system, turn it back on - nothing
> happens. The FPGA does'nt get programmed from the PROM. *IF at that
> point I right click on the CPLD in Impact, and select 'blank check',
> the CPLD starts 'working' and the FPGA gets programmed.

Try some other non-destructive operations - the most trivial would be
read idcode

It may be that the CPLD's jtag stage machine is waking up in a state
that keeps the CPLD from running; executing one of these operations
probably finished by putting it back into operational state.

As a guess, when it's in programming state, the ordinary I/O's would
all be high-Z.  Depending on pullup resistors, it's possible that
exiting from programming state to operating state could be producing a
clock edge necessary to start the process of loading your FPGA...

On Mar 1, 10:56 am, cs_post...@hotmail.com wrote:
> On Mar 1, 10:41 am, mtsuka...@gmail.com wrote:
>
> > The CPLD is connected to a xcf32 PROM and to a Xilinx V4 FPGA. All the
> > CPLD is doing is connecting the signals going from the PROM to the
> > FPGA - primarily the 'done' and 'd_in' pins. So, when I program the
> > CPLD, it works right away, and the FPGA gets programmed from the PROM.
> > If I turn off the POWER to the whole system, turn it back on - nothing
> > happens. The FPGA does'nt get programmed from the PROM. *IF at that
> > point I right click on the CPLD in Impact, and select 'blank check',
> > the CPLD starts 'working' and the FPGA gets programmed.
>
> Try some other non-destructive operations - the most trivial would be
> read idcode
>
> It may be that the CPLD's jtag stage machine is waking up in a state
> that keeps the CPLD from running; executing one of these operations
> probably finished by putting it back into operational state.
>
> As a guess, when it's in programming state, the ordinary I/O's would
> all be high-Z.  Depending on pullup resistors, it's possible that
> exiting from programming state to operating state could be producing a
> clock edge necessary to start the process of loading your FPGA...


Yea I actually tried doing 'id code' read, it didn't do anything,
didn't produce the same results as doing a 'blank check' or
reprogramming.

mtsukanov@gmail.com wrote:

> Yea I actually tried doing 'id code' read, it didn't do anything,
> didn't produce the same results as doing a 'blank check' or
> reprogramming.

check that you have the correct pullups/pulldowns on the JTAG pins.