74LVT transition times: How low can you go?

Joerg wrote:

>>> In an embedded application I need to slow down the /OE of a 74LVT244 
>>> so it turns tri-state fast but goes onto the bus slower, to avoid a 
>>> brief contention when addresses change. Is it ok for that family to 
>>> slow /OE by 200nsec or so via RC? It'll be the usual two resistor, 
>>> one diode and one cap deal. Want to avoid adding another Schmitt here.
>>
>> You can make a delay using something like 1G97.
> 
> I could also do it with a 74HC14 but I wanted to avoid more chips.

RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There 
is no real difference.

VLV

Vladimir Vassilevsky wrote:

> 
> 
> Joerg wrote:
> 
>>>> In an embedded application I need to slow down the /OE of a 74LVT244 
>>>> so it turns tri-state fast but goes onto the bus slower, to avoid a 
>>>> brief contention when addresses change. Is it ok for that family to 
>>>> slow /OE by 200nsec or so via RC? It'll be the usual two resistor, 
>>>> one diode and one cap deal. Want to avoid adding another Schmitt here.
>>>
>>>
>>> You can make a delay using something like 1G97.
>>
>>
>> I could also do it with a 74HC14 but I wanted to avoid more chips.
> 
> 
> RC and diode vs RC and 1G97. The diode is SOT-23 and so is 1G97. There 
> is no real difference.
> 

There is, however, a cost difference. A BAV70 runs you about a cent or 
two. But in this app that wouldn't matter (it usually does in my apps 
though).

-- 
Regards, Joerg

http://www.analogconsultants.com

Jim Granville wrote:

> Joerg wrote:
> 
>>
>> Or maybe I just place a couple Schmitt inverters to, as Jim put it, 
>> "do it right".
> 
> 
>  You could, (would cover more vendors), but to this Jim, using a part 
> with hysteresis IS 'doing it right'.
>  We've just designed in a Philips LVC2244 for that reason.
> 

Yes, that one stated Schmitts. Wonder why they still have those 
recommended tr/tf times in the data sheet. Oh well, I guess one can then 
happily ignore those. Unfortunately only NXP mentions Schmitts, TI 
doesn't unless I overlooked something. And NXP is out of stock :-(


>  To my mind, all logic should have hysteresis by default, but I
> do note that the new universal gates 1G57/58/97/98 all have hystersis.
> ( and the better CPLDs now have it selectable by pin )
> 

Agree, it all should. Would make life much easier.


>  If you need to start using 'fixup gates', have a look at those
> universal gate series.
> With one of those,  you should be able to save 2 if your passives.
> 

-- 
Regards, Joerg

http://www.analogconsultants.com

Joerg wrote:
>>  You could, (would cover more vendors), but to this Jim, using a part 
>> with hysteresis IS 'doing it right'.
>>  We've just designed in a Philips LVC2244 for that reason.
>>
> 
> Yes, that one stated Schmitts. Wonder why they still have those 
> recommended tr/tf times in the data sheet. Oh well, I guess one can then 
> happily ignore those.

See my earlier comment - they spec this so they can define the
tpd, and don't need to spend more time testing.

> Unfortunately only NXP mentions Schmitts, TI 
> doesn't unless I overlooked something. 

I just looked at IDT's offering, they spec :
VH Input Hysteresis VCC = 3.3V  100mV  typ


> And NXP is out of stock :-(

74LVC244A shows at Future and Digikey, in most packages  ?

Today package of choice seems to be TSSOP20. Not as easy
to solder as SO20, but a whole heap smaller/thinner.

-jg

Jim Granville wrote:

> Joerg wrote:
> 
>>>  You could, (would cover more vendors), but to this Jim, using a part 
>>> with hysteresis IS 'doing it right'.
>>>  We've just designed in a Philips LVC2244 for that reason.
>>>
>>
>> Yes, that one stated Schmitts. Wonder why they still have those 
>> recommended tr/tf times in the data sheet. Oh well, I guess one can 
>> then happily ignore those.
> 
> 
> See my earlier comment - they spec this so they can define the
> tpd, and don't need to spend more time testing.
> 
>> Unfortunately only NXP mentions Schmitts, TI doesn't unless I 
>> overlooked something. 
> 
> 
> I just looked at IDT's offering, they spec :
> VH Input Hysteresis VCC = 3.3V  100mV  typ
> 
> 
>> And NXP is out of stock :-(
> 
> 
> 74LVC244A shows at Future and Digikey, in most packages  ?
> 

Yes, indeed. I was looking at the one you had suggested further above, 
the LVC2244 where there is no stock. Still, it's somewhat uncomfortable 
to have to release only one manufacturer and ban others for the same 
chip. But it sure ain't the first time.

Thanks again for the hint. The LVC244 (from NXP) looks like a good chip.


> Today package of choice seems to be TSSOP20. Not as easy
> to solder as SO20, but a whole heap smaller/thinner.
> 

Yes, but I got used to it. Bought 3x glasses for lab work when TSSOP 
came out ;-)

Meantime I became a bit careful if a chip is not migrated to TSSOP 
because that could be an indicator that it's heading to lalaland.

-- 
Regards, Joerg

http://www.analogconsultants.com

CBFalconer wrote:
> 
> Is that a CMOS package?  If so, slow transition times will
> seriously increase the power consumption, and (if excessive) can
> actually destroy the chip.  The reason is that at intermediate
> levels both the pull-up and pull-down components are on, and are
> fighting each other.


'Destroy the chip' sounds unlikely ?.
Yes, there is a dIcc/dVin peak, but the worst devices I've seen
have this at a few mA - so that's a few milliwatts.

More common is sub mA peaks, and the better devices have this peak
in the uA - like the CPLD we are using here, which has a peak
value of 80uA.
A schmitt Ip gives two peaks,in the Icc/Vin curve, and avoids 
transistion oscillation.
-jg

On Thu, 01 Mar 2007 09:08:02 -0500, CBFalconer <cbfalconer@yahoo.com>
wrote:

>John Larkin wrote:
>> <notthisjoergsch@removethispacbell.net> wrote:
>> 
>>> Specsmanship seems to be on the decline. Philips/NXP is usually
>>> top notch but the family guide for their LVT series is, gasp,
>>> three pages short. Information about maximum transition times on
>>> inputs: Zilch.
>>>
>>> In an embedded application I need to slow down the /OE of a
>>> 74LVT244 so it turns tri-state fast but goes onto the bus slower,
>>> to avoid a brief contention when addresses change. Is it ok for
>>> that family to slow /OE by 200nsec or so via RC? It'll be the
>>> usual two resistor, one diode and one cap deal. Want to avoid
>>> adding another Schmitt here.
>> 
>> Sounds reasonable to me. Not a lot can go wrong here.
>
>Is that a CMOS package?  If so, slow transition times will
>seriously increase the power consumption, and (if excessive) can
>actually destroy the chip.  The reason is that at intermediate
>levels both the pull-up and pull-down components are on, and are
>fighting each other.

I think he's talking low duty cycles and fairly rapid slew through the
transition. I doubt the chip temperature would increase measurably.

I did recently post regarding a tiny logic triple buffer that was run
from +5 but driven from 3.3 volt logic. It was visibly hot on an ir
imager, +15c above ambient, with all three section inputs at +3.3. We
persuaded a single section to pull 45 mA by teasing the input voltage,
but it was probably oscillating too.

Never damaged one, though.

John

John Larkin wrote:


> I did recently post regarding a tiny logic triple buffer that was run
> from +5 but driven from 3.3 volt logic.  It was visibly hot on an ir
> imager, +15c above ambient, with all three section inputs at +3.3. We
> persuaded a single section to pull 45 mA by teasing the input voltage,
> but it was probably oscillating too.
> 
> Never damaged one, though.
> 

I did the same experiment with HCT04 gate powered from +5V. At 3.3V 
input, it was draining 0.5mA. At 2V at the input, the current was 1mA. 
The worst case consumption happened around 0.9V at the input, where it 
was about 4mA.

I don't see any problems here.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

On Mar 1, 1:08 pm, Joerg <notthisjoerg...@removethispacbell.net>
wrote:
> Vladimir Vassilevsky wrote:
>
> > Joerg wrote:
>
> >> In an embedded application I need to slow down the /OE of a 74LVT244
> >> so it turns tri-state fast but goes onto the bus slower, to avoid a
> >> brief contention when addresses change. Is it ok for that family to
> >> slow /OE by 200nsec or so via RC? It'll be the usual two resistor, one
> >> diode and one cap deal. Want to avoid adding another Schmitt here.
>
> > You can make a delay using something like 1G97.
>
> I could also do it with a 74HC14 but I wanted to avoid more chips.
>
> > But the 200ns seems like an awful long time. Why would you need that?
>
> I might get away with 100nsec. There is going to be some intricate
> address decoding, more than just a 688 and a 154.

To the OP, if you need 100 ns of delay to make your timing come out,
there may be a problem with the design.  I am sure you know what you
are doing, but typically the /OE is used on all bus devices as the
timing control and the /CE is used for selection.  Most devices
generate the /OE with enough timing margin relative to the address and
any CPU generated /CE controls that you shouldn't need to delay /OE.
You say your address decoding is very complex, is this what the /OE
delay is needed to compensate for?  Is there a way to speed up the
address decode?

I would like to understand what the diode based circuit is doing.  I
am primarily a digital designer and learned a long time ago that
analog components in a digital circuit usually meant someone was using
a bandaid or did not know how to do things "correctly".  I'm not
saying this is a true statement, but this was the view I was taught.
Is the diode in series with the driver (with a resistor in parallel
with the diode) along with a pull up resistor and the cap?  I would
like to see how this circuit would work just so I could use it if I
ever needed to.  I think that (in opposition to my training) there are
times when a simple analog circuit is ok to use in a digital design,
for example, a clock detector using a differentiator and an RC
filter.  But it is important to pay attention to voltage levels over
temperature to make sure enough voltage margin is preserved.

rickman wrote:


> I would like to understand what the diode based circuit is doing.  I
> am primarily a digital designer and learned a long time ago that
> analog components in a digital circuit usually meant someone was using
> a bandaid or did not know how to do things "correctly".

Good point. This is shamanism however it has to be done sometimes. 
Remember the pull-up resistor on Z80 clock input? The modern CPUs have 
the provision for picosecond timing adjustment on the signals.


   I'm not
> saying this is a true statement, but this was the view I was taught.
> Is the diode in series with the driver (with a resistor in parallel
> with the diode) along with a pull up resistor and the cap?  I would
> like to see how this circuit would work just so I could use it if I
> ever needed to.

Diode in series with the resistor plus the other resistor in parallel. 
Cap to the ground. The falling front is delayed, the raising front is 
also delayed but for less amount of time.


   I think that (in opposition to my training) there are
> times when a simple analog circuit is ok to use in a digital design,
> for example, a clock detector using a differentiator and an RC
> filter.  But it is important to pay attention to voltage levels over
> temperature to make sure enough voltage margin is preserved.

As usual, it is nothing wrong the tricks like that as long as one 
clearly knows what he is doing and what are the other implications.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com