Joerg wrote:>> And yet you believe him, thus accepting he's holier than you. > No, I believe in God.I hope you didn't mind my gentle dig. I've been there too, for a couple of decades, not spanning my childhood. Before you can believe in God, you believe in your ability to choose what to believe in. No matter what you tell yourself, it starts and ends with you. When you repudiate that, you repudiate your essential humanity. IME most pastors have more opinions than experience anyway. Why trust someone for advice on life, when they get paid *not* to live the kind of life *you* live?
74LVT transition times: How low can you go?
Started by ●February 28, 2007
Reply by ●March 2, 20072007-03-02
Reply by ●March 2, 20072007-03-02
Clifford Heath wrote:> Joerg wrote: > >>> And yet you believe him, thus accepting he's holier than you. >> >> No, I believe in God. > > > I hope you didn't mind my gentle dig. I've been there too, for > a couple of decades, not spanning my childhood. Before you can > believe in God, you believe in your ability to choose what to > believe in. No matter what you tell yourself, it starts and ends > with you. When you repudiate that, you repudiate your essential > humanity. IME most pastors have more opinions than experience > anyway. Why trust someone for advice on life, when they get paid > *not* to live the kind of life *you* live?We are lucky to have a pastor who lives his life very well IMHO. In our church we use the bible as the yardstick as to what is "well". Unfortunately a lot of other denominations don't. -- Regards, Joerg http://www.analogconsultants.com
Reply by ●March 2, 20072007-03-02
Jim Granville wrote:> CBFalconer wrote: >> Jim Granville wrote: >> >> ... snip ... >> >>> The other issue that can bite, is transistion oscillation. >>> Without a Schmitt, if you scoped the output at the 4mA peak, >>> you will see what I mean. That can cause real problems with >>> downstream devices - I've seen even unrelated pin drive have >>> edge-oscillation effects that needed external remedies. >> >> Actually a Schmidt trigger input can make things worse. Without >> it, a single CMOS inverter using a Vcc that allows a linear input >> bias can stabilize using just a large resistor from output to >> input. With it, the input voltage must be some sort of sawtooth, >> depending on the innate input capacitance. The half period will >> be the time needed for the input to rise (or fall) the hysteresis >> voltage. > > You've lost me here. I'm talking about unwanted transistion > oscillation, which can be in the 100's of MHz region in modern > devices. There is no feedback resistor, and a Schmitt IP does not > make transistion oscillation worse, it removes it. > > I think you are thinking of RC oscillators, or even Crystal > oscillators ( using unbuffered gates, HCU04 type) which are about > oscillators you'd try and do linear feedback, without real care.There is always feedback, possibly only via the capacitance between input and output. It is possible that the leakage current into the input pin is so small that the system becomes quiescent, but not too likely. That is why one normally ties unused inputs to ground (or Vcc). With, say 12V CMOS it is possible to bias the input pin so that both transistors are entirely off, and the system is stable. This is one of the curses of low Vcc CMOS logic - there is no real stable point where both input transistors are firmly off. -- Chuck F (cbfalconer at maineline dot net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net>
Reply by ●March 2, 20072007-03-02
CBFalconer wrote:> Jim Granville wrote: > >>CBFalconer wrote: >> >>>Jim Granville wrote: >>> >>>... snip ... >>> >>> >>>>The other issue that can bite, is transistion oscillation. >>>>Without a Schmitt, if you scoped the output at the 4mA peak, >>>>you will see what I mean. That can cause real problems with >>>>downstream devices - I've seen even unrelated pin drive have >>>>edge-oscillation effects that needed external remedies. >>> >>>Actually a Schmidt trigger input can make things worse. Without >>>it, a single CMOS inverter using a Vcc that allows a linear input >>>bias can stabilize using just a large resistor from output to >>>input. With it, the input voltage must be some sort of sawtooth, >>>depending on the innate input capacitance. The half period will >>>be the time needed for the input to rise (or fall) the hysteresis >>>voltage. >> >>You've lost me here. I'm talking about unwanted transistion >>oscillation, which can be in the 100's of MHz region in modern >>devices. There is no feedback resistor, and a Schmitt IP does not >>make transistion oscillation worse, it removes it. >> >>I think you are thinking of RC oscillators, or even Crystal >>oscillators ( using unbuffered gates, HCU04 type) which are about >>oscillators you'd try and do linear feedback, without real care. > > > There is always feedback, possibly only via the capacitance between > input and output. It is possible that the leakage current into the > input pin is so small that the system becomes quiescent, but not > too likely. That is why one normally ties unused inputs to ground > (or Vcc). With, say 12V CMOS it is possible to bias the input pin > so that both transistors are entirely off, and the system is > stable. This is one of the curses of low Vcc CMOS logic - there is > no real stable point where both input transistors are firmly off.You've moved even further from my transistion oscillation instance, but I'm lost as to what "both transistors are entirely off" can mean. I think you mean ONE transistor is entirely off (so no conduction?) - in a CMOS gate input structure, the only way to have BOTH off, is to remove the power! Yes, modern devices can have lower thresholds, but it's not as bad as you might think, on most logic devices. I've done a plot of an Atmel ATF1502BE CPLD, ( not your 45nm CPU, but in a quite modern Logic process ) With the Schmitt enabled, there are two peak currents. Vin AdderIcc -----+------------------------- <0.615 <+1uA ~Off 0.72 +6uA Conduction Tail 0.77 80uA Peak [Falling] 1.000 65uA Peak [Rising] 1.112 +6uA Conduction Tail >1.23 +1uA ~Off On this device, below 615mV, or above 1.23V, and there is effectively no CMOS P-N current path. Even the peaks are quite low, at 80uA and 65uA, and these are MUCH lower than a non Schmitt transfer ( IIRC ~45mA narrow Icc Peak ) Drive this from a 1.8V p-p sine-wave, and that averages +8uA of Icc adder. -jg
Reply by ●March 3, 20072007-03-03
On Mar 2, 4:27 pm, Joerg <notthisjoerg...@removethispacbell.net> wrote:> rickman wrote: > > Regardless of the name, all you need to do to prevent contention is > > for the controller to delay enabling the next device for a period > > after it disables the last device. Why is the controller not handing > > this? That would be the "correct" digital approach to dealing with > > this problem. > > Well, we opted for a bare bones bus where the adresses do that :-)Maybe I still don't understand what you are doing. Are you saying that the controller does not generate a timing strobe at all? Even if there is a single timing strobe combined with the address lines, that would work fine. The controller just has to deactivate the enable long enough for the address to change and the decoders to get stable inputs. If you are not using a timing strobe (enable) then you are asking for trouble. The decoders can generate glitches that can cause the receiving circuits to think they saw an enable with no clock pulses. This can cause all sorts of malfunctions. I don't know about your specific circuits, but I would not try this with or without the analog delays in the timing.> That's why I like Schmitts. Unless I want to use an logic inverter as a > linear amp...But you still have to understand the digital circuitry and how to generate correct timing. Or am I missing something about your design?> Thou shalt not go by the typical Rdson versus Vgs graph but always by > the guaranteed values.Yes, I am sure the designer learned a bit about that. I am surprised it took a process change to cause failures actually.
Reply by ●March 3, 20072007-03-03
In article <1172897278.348695.307870@h3g2000cwc.googlegroups.com>, rickman says...> On Mar 2, 4:27 pm, Joerg <notthisjoerg...@removethispacbell.net> > wrote: > > Thou shalt not go by the typical Rdson versus Vgs graph but always by > > the guaranteed values. > > Yes, I am sure the designer learned a bit about that. I am surprised > it took a process change to cause failures actually.I saw a design a few years back where an RC between two Schmidt input inverters was used as a delay element. Years into production they started getting failures. It turned out that the timing was ultimately controlled not by the RC but by the current drive capabilities of the inverter. They had changed to an equivalent part from another supplier and it's drive current limit was different. Robert -- Posted via a free Usenet account from http://www.teranews.com
Reply by ●March 3, 20072007-03-03
"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message news:cU%Fh.4715$P47.3112@newssvr22.news.prodigy.net...> > > rickman wrote: > > >> Heck, I saw a circuit that simply used a FET to control the current >> through an LED. > > Great. I have seen bunch of leds connected in parallel. Another good one > is driving a led by logic '1' directly from a chip. But the best solution > I ever heard of is using comparator as opamp in the measurement circuit! > And after that somebody complains about the software... > > Vladimir Vassilevsky > > DSP and Mixed Signal Design Consultant > > http://www.abvolt.comNot wishing to set you off but I'd take a guess that these analog 'solutions' were implemented by 'digital/software' engineers....... DNA
Reply by ●March 3, 20072007-03-03
rickman wrote:> On Mar 2, 4:27 pm, Joerg <notthisjoerg...@removethispacbell.net> > wrote: > >>rickman wrote: >> >>>Regardless of the name, all you need to do to prevent contention is >>>for the controller to delay enabling the next device for a period >>>after it disables the last device. Why is the controller not handing >>>this? That would be the "correct" digital approach to dealing with >>>this problem. >> >>Well, we opted for a bare bones bus where the adresses do that :-) > > > Maybe I still don't understand what you are doing. Are you saying > that the controller does not generate a timing strobe at all? Even if > there is a single timing strobe combined with the address lines, that > would work fine. The controller just has to deactivate the enable > long enough for the address to change and the decoders to get stable > inputs. If you are not using a timing strobe (enable) then you are > asking for trouble. The decoders can generate glitches that can cause > the receiving circuits to think they saw an enable with no clock > pulses. This can cause all sorts of malfunctions. I don't know about > your specific circuits, but I would not try this with or without the > analog delays in the timing. >Poor man's strobe, via the enable inputs of several HC688 decoders :-))) That works, as long as wait times are maintained and no data transfer happens unless the addresses are held stable.> > >>That's why I like Schmitts. Unless I want to use an logic inverter as a >>linear amp... > > > But you still have to understand the digital circuitry and how to > generate correct timing. Or am I missing something about your > design? >Yes, one has to. That's why I like to run busses with zero contention, not even for a few nsec. Some may say it's ok for a short time sliver but my take is that it isn't meant to be and it also generates EMI headaches. Or at least EMI worries. I don't want the client to come back from UL with a black eye because this bus caused a few peaks to stick out beyond class B limits.> > >>Thou shalt not go by the typical Rdson versus Vgs graph but always by >>the guaranteed values. > > > Yes, I am sure the designer learned a bit about that. I am surprised > it took a process change to cause failures actually. > >-- Regards, Joerg http://www.analogconsultants.com
Reply by ●March 3, 20072007-03-03
Genome wrote:> "Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message > news:cU%Fh.4715$P47.3112@newssvr22.news.prodigy.net... > >> >>rickman wrote: >> >> >> >>>Heck, I saw a circuit that simply used a FET to control the current >>>through an LED. >> >>Great. I have seen bunch of leds connected in parallel. Another good one >>is driving a led by logic '1' directly from a chip. But the best solution >>I ever heard of is using comparator as opamp in the measurement circuit! >>And after that somebody complains about the software... >> >>Vladimir Vassilevsky >> >>DSP and Mixed Signal Design Consultant >> >>http://www.abvolt.com > > > Not wishing to set you off but I'd take a guess that these analog > 'solutions' were implemented by 'digital/software' engineers....... >Sometimes they are cooked up by very cost-conscious all-round designers. My "mentor circuit" was a product from your country, the Datong RF-clipper (it clips audio without intermod). They used CD4000 logic chips in analog fashion all over the place. And I guess they made tons of money. In fact, these things were so great that a rock guitarist absolutely wanted to keep mine after I gave it to him for a week. He was blown away, said he's never heard the rafters shake and the glass rattle so good when playing "Stairway to Heaven". After I told him that I really wanted it back he ordered one the next day. -- Regards, Joerg http://www.analogconsultants.com
Reply by ●March 3, 20072007-03-03
CBFalconer wrote:> Jim Granville wrote: > >>CBFalconer wrote: >> >>>Jim Granville wrote: >>> >>>... snip ... >>> >>> >>>>The other issue that can bite, is transistion oscillation. >>>>Without a Schmitt, if you scoped the output at the 4mA peak, >>>>you will see what I mean. That can cause real problems with >>>>downstream devices - I've seen even unrelated pin drive have >>>>edge-oscillation effects that needed external remedies. >>> >>>Actually a Schmidt trigger input can make things worse. Without >>>it, a single CMOS inverter using a Vcc that allows a linear input >>>bias can stabilize using just a large resistor from output to >>>input. With it, the input voltage must be some sort of sawtooth, >>>depending on the innate input capacitance. The half period will >>>be the time needed for the input to rise (or fall) the hysteresis >>>voltage. >> >>You've lost me here. I'm talking about unwanted transistion >>oscillation, which can be in the 100's of MHz region in modern >>devices. There is no feedback resistor, and a Schmitt IP does not >>make transistion oscillation worse, it removes it. >> >>I think you are thinking of RC oscillators, or even Crystal >>oscillators ( using unbuffered gates, HCU04 type) which are about >>oscillators you'd try and do linear feedback, without real care. > > > There is always feedback, possibly only via the capacitance between > input and output. It is possible that the leakage current into the > input pin is so small that the system becomes quiescent, but not > too likely. That is why one normally ties unused inputs to ground > (or Vcc). With, say 12V CMOS it is possible to bias the input pin > so that both transistors are entirely off, and the system is > stable. This is one of the curses of low Vcc CMOS logic - there is > no real stable point where both input transistors are firmly off. >That can also be a blessing when you want to make a really cheap amp. -- Regards, Joerg http://www.analogconsultants.com
