Ulf Samuelsson wrote:> Subject: Flash mcu with SPI slave capable of 16MHz operation? > > > >>I guess none available :( >> >>all seem limit to clock/4 or something >> >>but maybe I have missed some good part? >> >>Antti >> > > Why need a flash MCU? Protection? > An AT91SAM9261 has 160 kB of internal SRAM which > can be used for code & data. > It can load the SRAM from a cheap 1 Mbit serial flash. > > Running the bus at 96 MHz you have 96/16 = 6 times > overclocking which should be good enough! > > Your CPU will run at 200 MIPS+ as well from the TCM.Hi Ulf, Antti since came back with another detail - a $3US budget ;) - but while you are here, what is the MAX Slave clock speed for the AT32UC3A0512 ? Antti: I did find the infineon XC2200 specs this [SSC/SPI/QSPI (synchronous serial channel with or without data buffer) � maximum baud rate in slave mode: fSYS � maximum baud rate in master mode: fSYS / 2 � number of data bits programmable from 1 to 63, more with explicit stop condition � MSB or LSB first � optional control of slave select signals] Not sure if that is a typo, as they claim faster Slave than Master ?, - out of step with everyone else. Nice part/peripheral, but the XC2200 family are starting at the top, and releasing downwards (as is the AT32UC3A0512 ), so neither are going to hit $3 until smaller ones come along... -jg
Flash mcu with SPI slave capable of 16MHz operation?
Started by ●May 7, 2007
Reply by ●May 7, 20072007-05-07
Reply by ●May 9, 20072007-05-09
"Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet news:463eeb29$1@clear.net.nz...> Antti wrote: >> I guess none available :( >> >> all seem limit to clock/4 or something >> >> but maybe I have missed some good part? >>>> The AT32UC3A0512 looks fast in master, but I did not > see a fMAX in slave mode. > AT91SAM9260 info suggests ~32ns in slave, but lacks any > CLK ratio specs, and there must be some. >My firends at Atmel Nantes says that the SPI slave will work up to CPUCLK/2, so 32 MHz should be possible with the AT32UC3A0512. While this wont meet the $3, the AT32UC3B family should maybe be in the right price range, probably not in single qty though. -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
Reply by ●May 9, 20072007-05-09
Ulf Samuelsson wrote:> "Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet > news:463eeb29$1@clear.net.nz... > >>Antti wrote: >> >>>I guess none available :( >>> >>>all seem limit to clock/4 or something >>> >>>but maybe I have missed some good part? >>> > > >>>The AT32UC3A0512 looks fast in master, but I did not >> >>see a fMAX in slave mode. >>AT91SAM9260 info suggests ~32ns in slave, but lacks any >>CLK ratio specs, and there must be some. >> > > > > My firends at Atmel Nantes says that the SPI slave will work up to > CPUCLK/2, so 32 MHz should be possible with the AT32UC3A0512. > While this wont meet the $3, the AT32UC3B family should maybe be > in the right price range, probably not in single qty though.Thanks Ulf. Is this true of all Atmel 32 bit SPI peripherals ? (SAM7 and SAM9 ? ). Where I have seen a 2x ceiling before, it is sometimes qualified with Tsu,Th,Jitter, and duty cycle margins, to be appx 2.5x as a 'practical ceiling'. It may be that some of the 4x SPI specs are just rounding that again. Any schedule for the AT32UC3B family yet ? I'd imagine Antti's BOM target is not single Qty, as worrying about that detail of price only matters for > 10K levels. -jg
Reply by ●May 10, 20072007-05-10
On 10 Mai, 00:29, Jim Granville <no.s...@designtools.maps.co.nz> wrote:> Ulf Samuelsson wrote: > > "Jim Granville" <no.s...@designtools.maps.co.nz> skrev i meddelandet > >news:463eeb29$1@clear.net.nz... > > >>Antti wrote: > > >>>I guess none available :( > > >>>all seem limit to clock/4 or something > > >>>but maybe I have missed some good part? > > >>>The AT32UC3A0512 looks fast in master, but I did not > > >>see a fMAX in slave mode. > >>AT91SAM9260 info suggests ~32ns in slave, but lacks any > >>CLK ratio specs, and there must be some. > > > My firends at Atmel Nantes says that the SPI slave will work up to > > CPUCLK/2, so 32 MHz should be possible with the AT32UC3A0512. > > While this wont meet the $3, the AT32UC3B family should maybe be > > in the right price range, probably not in single qty though. > > Thanks Ulf. Is this true of all Atmel 32 bit SPI peripherals ? > (SAM7 and SAM9 ? ). > Where I have seen a 2x ceiling before, it > is sometimes qualified with Tsu,Th,Jitter, and duty cycle margins, > to be appx 2.5x as a 'practical ceiling'. It may be that some of > the 4x SPI specs are just rounding that again. > > Any schedule for the AT32UC3B family yet ? > > I'd imagine Antti's BOM target is not single Qty, as worrying about that > detail of price only matters for > 10K levels. > > -jg- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -Jim, your guess is very correct. BOM cost difference of 0.80 USD matter at qty >10K Antti, who also looks forward to see more AVR32 flash chips
Reply by ●May 11, 20072007-05-11
>> >> Any schedule for the AT32UC3B family yet ? >> >> I'd imagine Antti's BOM target is not single Qty, as worrying about that >> detail of price only matters for > 10K levels. > > Jim, > your guess is very correct. > BOM cost difference of 0.80 USD matter at qty >10K >The AVR32 SPI implementation does not synchronize the input clock with the internal clock. Instead the input clock will clock the flip flops in the SPI shift register and synchronization is done when the complete byte is read/written to holding register. Looking at the AT91 SPI block diagram shows that this is the same. No synchronization of the SPI clock in slave mode. I guess that any SAM7S should do as well then.> Antti, > who also looks forward to see more AVR32 flash chips > >Many are!!! -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
Reply by ●May 11, 20072007-05-11
Ulf Samuelsson wrote:> The AVR32 SPI implementation does not synchronize the > input clock with the internal clock. > Instead the input clock will clock the flip flops > in the SPI shift register and synchronization is > done when the complete byte is read/written to holding register. > Looking at the AT91 SPI block diagram shows that this is the same. > No synchronization of the SPI clock in slave mode. > > I guess that any SAM7S should do as well then.So, then where-from the SYSCLK/2 limit ?. What you describe should be able to clock faster on the slave ? -jg
Reply by ●May 11, 20072007-05-11
"Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet news:46440fcd$1@clear.net.nz...> Ulf Samuelsson wrote: >> The AVR32 SPI implementation does not synchronize the >> input clock with the internal clock. >> Instead the input clock will clock the flip flops >> in the SPI shift register and synchronization is >> done when the complete byte is read/written to holding register. >> Looking at the AT91 SPI block diagram shows that this is the same. >> No synchronization of the SPI clock in slave mode. >> >> I guess that any SAM7S should do as well then. > > So, then where-from the SYSCLK/2 limit ?. > What you describe should be able to clock faster on the slave ? > > -jg >I do not know how the synchronization for the holding register works... -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB