Forums

Cyclone 3 Starter Board Question

Started by fpgabuilder May 31, 2007
Anyone know how the USB Blaster cable loads data to the C3 fpga on the
board?  The schematic shows a CPLD between the FPGA and the USB port.
There is a USB to parallel chip between the cpld and the usb port.
But I do not see any serial or parallel data going to the fpga.

I wish Altera added more details to the starter kit documentation.
There is all this source code but it is encrypted.  So  cannot even
look at that.

TIA
-sanjay

On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
> Anyone know how the USB Blaster cable loads data to the C3 fpga on the > board? The schematic shows a CPLD between the FPGA and the USB port. > There is a USB to parallel chip between the cpld and the usb port. > But I do not see any serial or parallel data going to the fpga. > > I wish Altera added more details to the starter kit documentation. > There is all this source code but it is encrypted. So cannot even > look at that. > > TIA > -sanjay
That CPLD along with the FT245 is the "embedded USB Blaster". You won't see any lines to the FPGA except for the JTAG leads. (I found the JTAG lines on the schematic - look again.) The documentation looked pretty complete to me. For the Xilinx board, the page of schematic with the USB loader is *missing*, and that area of the layout is obscured. Both companies used to ship separate dongles with their eval boards. But the plastic case of the dongle is the most expensive part, followed by the JTAG leads. By leaving those out, they can add the USB programmer for almost nothing. It's possible that both companies contracted out the design of their USB programming pods, so they can't (legally) distribute the information on the device. (Both companies make a ton of money selling IP; you have to understand that they will respect the IP rights of others.) Do a web search. There are a number of people actively tring to reverse engineer both dongles. At least until they discover hat they're spending 100's of hours to duplicate a gizmo that can be had for $50... G.
On May 31, 4:42 pm, ghel...@lycos.com wrote:
> On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > board? The schematic shows a CPLD between the FPGA and the USB port. > > There is a USB to parallel chip between the cpld and the usb port. > > But I do not see any serial or parallel data going to the fpga. > > > I wish Altera added more details to the starter kit documentation. > > There is all this source code but it is encrypted. So cannot even > > look at that. > > > TIA > > -sanjay > > That CPLD along with the FT245 is the "embedded USB Blaster". You > won't see any lines to the FPGA except for the JTAG leads. (I found > the JTAG lines on the schematic - look again.) > > The documentation looked pretty complete to me. For the Xilinx board, > the page of schematic with the USB loader is *missing*, and that area > of the layout is obscured. > > Both companies used to ship separate dongles with their eval boards. > But the plastic case of the dongle is the most expensive part, > followed by the JTAG leads. By leaving those out, they can add the > USB programmer for almost nothing. > > It's possible that both companies contracted out the design of their > USB programming pods, so they can't (legally) distribute the > information on the device. (Both companies make a ton of money > selling IP; you have to understand that they will respect the IP > rights of others.) > > Do a web search. There are a number of people actively tring to > reverse engineer both dongles. At least until they discover hat > they're spending 100's of hours to duplicate a gizmo that can be had > for $50... > > G.
Sorry I wasn't clear. By data I did not mean the configuration or jtag stream. Not sure if you are familiar with the C3 starter board. But they have something called control panel, which you use to test the dram access besides other things. You can read and write to the sdram. Store entire files, etc. And the only host interface I see for this is the usb interface. But I do not see any data lines. So that is what I mean by data. Please let me know where to look if you find that in their documentation. Thanks. Best, -sanjay
On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
> On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > There is a USB to parallel chip between the cpld and the usb port. > > > But I do not see any serial or parallel data going to the fpga. > > > > I wish Altera added more details to the starter kit documentation. > > > There is all this source code but it is encrypted. So cannot even > > > look at that. > > > > TIA > > > -sanjay > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > won't see any lines to the FPGA except for the JTAG leads. (I found > > the JTAG lines on the schematic - look again.) > > > The documentation looked pretty complete to me. For the Xilinx board, > > the page of schematic with the USB loader is *missing*, and that area > > of the layout is obscured. > > > Both companies used to ship separate dongles with their eval boards. > > But the plastic case of the dongle is the most expensive part, > > followed by the JTAG leads. By leaving those out, they can add the > > USB programmer for almost nothing. > > > It's possible that both companies contracted out the design of their > > USB programming pods, so they can't (legally) distribute the > > information on the device. (Both companies make a ton of money > > selling IP; you have to understand that they will respect the IP > > rights of others.) > > > Do a web search. There are a number of people actively tring to > > reverse engineer both dongles. At least until they discover hat > > they're spending 100's of hours to duplicate a gizmo that can be had > > for $50... > > > G. > > Sorry I wasn't clear. By data I did not mean the configuration or > jtag stream. Not sure if you are familiar with the C3 starter board. > But they have something called control panel, which you use to test > the dram access besides other things. You can read and write to the > sdram. Store entire files, etc. And the only host interface I see > for this is the usb interface. But I do not see any data lines. So > that is what I mean by data. > > Please let me know where to look if you find that in their > documentation. > > Thanks. > Best, > -sanjay- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -
well, there is no need for more then JTAG lines ;) Altera FPGAs can have user logic in fabric connected to the JTAG TAP, so the same JTAG pins can be used to talk to the user app as well. this is how signaltap works as example Antti
On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > But I do not see any serial or parallel data going to the fpga. > > > > > I wish Altera added more details to the starter kit documentation. > > > > There is all this source code but it is encrypted. So cannot even > > > > look at that. > > > > > TIA > > > > -sanjay > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > the JTAG lines on the schematic - look again.) > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > the page of schematic with the USB loader is *missing*, and that area > > > of the layout is obscured. > > > > Both companies used to ship separate dongles with their eval boards. > > > But the plastic case of the dongle is the most expensive part, > > > followed by the JTAG leads. By leaving those out, they can add the > > > USB programmer for almost nothing. > > > > It's possible that both companies contracted out the design of their > > > USB programming pods, so they can't (legally) distribute the > > > information on the device. (Both companies make a ton of money > > > selling IP; you have to understand that they will respect the IP > > > rights of others.) > > > > Do a web search. There are a number of people actively tring to > > > reverse engineer both dongles. At least until they discover hat > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > for $50... > > > > G. > > > Sorry I wasn't clear. By data I did not mean the configuration or > > jtag stream. Not sure if you are familiar with the C3 starter board. > > But they have something called control panel, which you use to test > > the dram access besides other things. You can read and write to the > > sdram. Store entire files, etc. And the only host interface I see > > for this is the usb interface. But I do not see any data lines. So > > that is what I mean by data. > > > Please let me know where to look if you find that in their > > documentation. > > > Thanks. > > Best, > > -sanjay- Zitierten Text ausblenden - > > > - Zitierten Text anzeigen - > > well, there is no need for more then JTAG lines ;) > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > so the same JTAG pins can be used to talk to the user app as well. > this is how signaltap works as example > > Antti
Thanks Antii. I had suspected this. And I think this is a cool feature for low bandwidth operations such as serial communication. I am thinking how can I use this in my application? Please let me know if you have any pointers. TIA. -sanjay
On Jun 1, 7:34 am, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
> On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > > But I do not see any serial or parallel data going to the fpga. > > > > > > I wish Altera added more details to the starter kit documentation. > > > > > There is all this source code but it is encrypted. So cannot even > > > > > look at that. > > > > > > TIA > > > > > -sanjay > > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > > the JTAG lines on the schematic - look again.) > > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > > the page of schematic with the USB loader is *missing*, and that area > > > > of the layout is obscured. > > > > > Both companies used to ship separate dongles with their eval boards. > > > > But the plastic case of the dongle is the most expensive part, > > > > followed by the JTAG leads. By leaving those out, they can add the > > > > USB programmer for almost nothing. > > > > > It's possible that both companies contracted out the design of their > > > > USB programming pods, so they can't (legally) distribute the > > > > information on the device. (Both companies make a ton of money > > > > selling IP; you have to understand that they will respect the IP > > > > rights of others.) > > > > > Do a web search. There are a number of people actively tring to > > > > reverse engineer both dongles. At least until they discover hat > > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > > for $50... > > > > > G. > > > > Sorry I wasn't clear. By data I did not mean the configuration or > > > jtag stream. Not sure if you are familiar with the C3 starter board. > > > But they have something called control panel, which you use to test > > > the dram access besides other things. You can read and write to the > > > sdram. Store entire files, etc. And the only host interface I see > > > for this is the usb interface. But I do not see any data lines. So > > > that is what I mean by data. > > > > Please let me know where to look if you find that in their > > > documentation. > > > > Thanks. > > > Best, > > > -sanjay- Zitierten Text ausblenden - > > > > - Zitierten Text anzeigen - > > > well, there is no need for more then JTAG lines ;) > > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > > so the same JTAG pins can be used to talk to the user app as well. > > this is how signaltap works as example
Jtag can scan all boundary cells (most I/O pins) and using them to drive external devices as well.
> > > Antti > > Thanks Antii. I had suspected this. And I think this is a cool > feature for low bandwidth operations such as serial communication.
As long as the serial pins are in the boundary scan chain, which is usually the case. However, sometimes the internal buffers get in the way of boundary scans.
> I am thinking how can I use this in my application?
Build (or buy) your jtag scan engine, like many of us do.
> Please let me know > if you have any pointers. > > TIA. > -sanjay
On 1 Jun., 17:53, linnix <m...@linnix.info-for.us> wrote:
> On Jun 1, 7:34 am, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > > > But I do not see any serial or parallel data going to the fpga. > > > > > > > I wish Altera added more details to the starter kit documentation. > > > > > > There is all this source code but it is encrypted. So cannot even > > > > > > look at that. > > > > > > > TIA > > > > > > -sanjay > > > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > > > the JTAG lines on the schematic - look again.) > > > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > > > the page of schematic with the USB loader is *missing*, and that area > > > > > of the layout is obscured. > > > > > > Both companies used to ship separate dongles with their eval boards. > > > > > But the plastic case of the dongle is the most expensive part, > > > > > followed by the JTAG leads. By leaving those out, they can add the > > > > > USB programmer for almost nothing. > > > > > > It's possible that both companies contracted out the design of their > > > > > USB programming pods, so they can't (legally) distribute the > > > > > information on the device. (Both companies make a ton of money > > > > > selling IP; you have to understand that they will respect the IP > > > > > rights of others.) > > > > > > Do a web search. There are a number of people actively tring to > > > > > reverse engineer both dongles. At least until they discover hat > > > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > > > for $50... > > > > > > G. > > > > > Sorry I wasn't clear. By data I did not mean the configuration or > > > > jtag stream. Not sure if you are familiar with the C3 starter board. > > > > But they have something called control panel, which you use to test > > > > the dram access besides other things. You can read and write to the > > > > sdram. Store entire files, etc. And the only host interface I see > > > > for this is the usb interface. But I do not see any data lines. So > > > > that is what I mean by data. > > > > > Please let me know where to look if you find that in their > > > > documentation. > > > > > Thanks. > > > > Best, > > > > -sanjay- Zitierten Text ausblenden - > > > > > - Zitierten Text anzeigen - > > > > well, there is no need for more then JTAG lines ;) > > > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > > > so the same JTAG pins can be used to talk to the user app as well. > > > this is how signaltap works as example > > Jtag can scan all boundary cells (most I/O pins) and using them to > drive external devices as well. > > > > > > Antti > > > Thanks Antii. I had suspected this. And I think this is a cool > > feature for low bandwidth operations such as serial communication. > > As long as the serial pins are in the boundary scan chain, which is > usually the case. However, sometimes the internal buffers get in the > way of boundary scans. > > > I am thinking how can I use this in my application? > > Build (or buy) your jtag scan engine, like many of us do. > > > > > Please let me know > > if you have any pointers. > > > TIA. > > -sanjay- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -
hm, when you use the "JTAG in FPGA fabric" approuch then JTAG boundary scan chain is NOT USED. so it doesnt matter at all how the boundary scan is implemented or if it even exists. "custom instructions" are handled by FPGA fabric the speed depends on the JTAG master, it may reach 40MHz+ Antti
On Jun 1, 10:12 am, Antti <Antti.Luk...@googlemail.com> wrote:
> On 1 Jun., 17:53, linnix <m...@linnix.info-for.us> wrote: > > > > > On Jun 1, 7:34 am, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > > > > But I do not see any serial or parallel data going to the fpga. > > > > > > > > I wish Altera added more details to the starter kit documentation. > > > > > > > There is all this source code but it is encrypted. So cannot even > > > > > > > look at that. > > > > > > > > TIA > > > > > > > -sanjay > > > > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > > > > the JTAG lines on the schematic - look again.) > > > > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > > > > the page of schematic with the USB loader is *missing*, and that area > > > > > > of the layout is obscured. > > > > > > > Both companies used to ship separate dongles with their eval boards. > > > > > > But the plastic case of the dongle is the most expensive part, > > > > > > followed by the JTAG leads. By leaving those out, they can add the > > > > > > USB programmer for almost nothing. > > > > > > > It's possible that both companies contracted out the design of their > > > > > > USB programming pods, so they can't (legally) distribute the > > > > > > information on the device. (Both companies make a ton of money > > > > > > selling IP; you have to understand that they will respect the IP > > > > > > rights of others.) > > > > > > > Do a web search. There are a number of people actively tring to > > > > > > reverse engineer both dongles. At least until they discover hat > > > > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > > > > for $50... > > > > > > > G. > > > > > > Sorry I wasn't clear. By data I did not mean the configuration or > > > > > jtag stream. Not sure if you are familiar with the C3 starter board. > > > > > But they have something called control panel, which you use to test > > > > > the dram access besides other things. You can read and write to the > > > > > sdram. Store entire files, etc. And the only host interface I see > > > > > for this is the usb interface. But I do not see any data lines. So > > > > > that is what I mean by data. > > > > > > Please let me know where to look if you find that in their > > > > > documentation. > > > > > > Thanks. > > > > > Best, > > > > > -sanjay- Zitierten Text ausblenden - > > > > > > - Zitierten Text anzeigen - > > > > > well, there is no need for more then JTAG lines ;) > > > > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > > > > so the same JTAG pins can be used to talk to the user app as well. > > > > this is how signaltap works as example > > > Jtag can scan all boundary cells (most I/O pins) and using them to > > drive external devices as well. > > > > > Antti > > > > Thanks Antii. I had suspected this. And I think this is a cool > > > feature for low bandwidth operations such as serial communication. > > > As long as the serial pins are in the boundary scan chain, which is > > usually the case. However, sometimes the internal buffers get in the > > way of boundary scans. > > > > I am thinking how can I use this in my application? > > > Build (or buy) your jtag scan engine, like many of us do. > > > > Please let me know > > > if you have any pointers. > > > > TIA. > > > -sanjay- Zitierten Text ausblenden - > > > - Zitierten Text anzeigen -- Zitierten Text ausblenden - > > > - Zitierten Text anzeigen - > > hm, > when you use the "JTAG in FPGA fabric" approuch then JTAG boundary > scan chain is NOT USED.
There are certainly many ways to configurate the FPGA. For development and temperatory configuration, you can jtag into the FPGA directly. However, real app configuration is usually stored in external flash chip. A typical jtag tool would program the external flash chip via boundary scan.
On Jun 1, 10:30 am, linnix <m...@linnix.info-for.us> wrote:
> On Jun 1, 10:12 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 1 Jun., 17:53, linnix <m...@linnix.info-for.us> wrote: > > > > On Jun 1, 7:34 am, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > > > > > But I do not see any serial or parallel data going to the fpga. > > > > > > > > > I wish Altera added more details to the starter kit documentation. > > > > > > > > There is all this source code but it is encrypted. So cannot even > > > > > > > > look at that. > > > > > > > > > TIA > > > > > > > > -sanjay > > > > > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > > > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > > > > > the JTAG lines on the schematic - look again.) > > > > > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > > > > > the page of schematic with the USB loader is *missing*, and that area > > > > > > > of the layout is obscured. > > > > > > > > Both companies used to ship separate dongles with their eval boards. > > > > > > > But the plastic case of the dongle is the most expensive part, > > > > > > > followed by the JTAG leads. By leaving those out, they can add the > > > > > > > USB programmer for almost nothing. > > > > > > > > It's possible that both companies contracted out the design of their > > > > > > > USB programming pods, so they can't (legally) distribute the > > > > > > > information on the device. (Both companies make a ton of money > > > > > > > selling IP; you have to understand that they will respect the IP > > > > > > > rights of others.) > > > > > > > > Do a web search. There are a number of people actively tring to > > > > > > > reverse engineer both dongles. At least until they discover hat > > > > > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > > > > > for $50... > > > > > > > > G. > > > > > > > Sorry I wasn't clear. By data I did not mean the configuration or > > > > > > jtag stream. Not sure if you are familiar with the C3 starter board. > > > > > > But they have something called control panel, which you use to test > > > > > > the dram access besides other things. You can read and write to the > > > > > > sdram. Store entire files, etc. And the only host interface I see > > > > > > for this is the usb interface. But I do not see any data lines. So > > > > > > that is what I mean by data. > > > > > > > Please let me know where to look if you find that in their > > > > > > documentation. > > > > > > > Thanks. > > > > > > Best, > > > > > > -sanjay- Zitierten Text ausblenden - > > > > > > > - Zitierten Text anzeigen - > > > > > > well, there is no need for more then JTAG lines ;) > > > > > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > > > > > so the same JTAG pins can be used to talk to the user app as well. > > > > > this is how signaltap works as example > > > > Jtag can scan all boundary cells (most I/O pins) and using them to > > > drive external devices as well. > > > > > > Antti > > > > > Thanks Antii. I had suspected this. And I think this is a cool > > > > feature for low bandwidth operations such as serial communication. > > > > As long as the serial pins are in the boundary scan chain, which is > > > usually the case. However, sometimes the internal buffers get in the > > > way of boundary scans. > > > > > I am thinking how can I use this in my application? > > > > Build (or buy) your jtag scan engine, like many of us do. > > > > > Please let me know > > > > if you have any pointers. > > > > > TIA. > > > > -sanjay- Zitierten Text ausblenden - > > > > - Zitierten Text anzeigen -- Zitierten Text ausblenden - > > > > - Zitierten Text anzeigen - > > > hm, > > when you use the "JTAG in FPGA fabric" approuch then JTAG boundary > > scan chain is NOT USED. > > There are certainly many ways to configurate the FPGA. For > development and temperatory configuration, you can jtag into the FPGA > directly. However, real app configuration is usually stored in > external flash chip. A typical jtag tool would program the external > flash chip via boundary scan.
I think the question is how to use the jtag port to read and write to the configured logic inside the fpga. This is different from configuring the fpgas. I did find the answer. Altera has virtual jtag interface (sld_virtual_jtag). Thanks for the discussion. Best, -sanjay