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Xilinx V4 Custom IP

Started by Unknown July 13, 2007
I am trying to write a simple custom IP to get started.  I just want
to control the LED on my evaluation board.  I want to be able to write
a custom IP to prove to myself I am doing it correctly instead of
using the IP provided.

I am using a Memec V4 UltraController II eval board and EDK 9.1 SP2.
I created a template IP using EDK and then wrote my VHDL code to
control the LEDs.  The problem is I have no control over the LEDs.

In my led.vhd file I added to my entity and architecture:
    --USER ports added here
    pLED1									: out std_logic;
    pLED2									: out std_logic;
    pLED3									: out std_logic;

Then in user logic I added some internal signals to my architecture:

 signal iLED1									 : std_logic := '1';
  signal iLED2									 : std_logic := '0';
  signal iLED3									 : std_logic := '0';

And finally I added some assignments at the end of the architecture:
  pLED1 <= iLED1;
  pLED2 <= iLED2;
  pLED3 <= slv_reg0(2);

slv_reg0 is a register that can be written to and read over the OPB.
The slv_reg0 can be read and written through  XMD, but the LEDs do not
change.  Also using the default signal values, LED1 & LED2 should have
different states, but all 3 LEDs have the same state.

For completion I added:

Net fpga_0_LED1_pin LOC = D13 | IOSTANDARD = LVCMOS25;
Net fpga_0_LED2_pin LOC = D12 | IOSTANDARD = LVCMOS25;
Net fpga_0_LED3_pin LOC = D11 | IOSTANDARD = LVCMOS25;

to the system.ucf file.  And I added:

PORT fpga_0_LED1_pin = fpga_0_LED1, DIR = O
 PORT fpga_0_LED2_pin = fpga_0_LED2, DIR = O
 PORT fpga_0_LED3_pin = fpga_0_LED3, DIR = O

and

BEGIN opb_leds
 PARAMETER INSTANCE = opb_leds_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x73c00000
 PARAMETER C_HIGHADDR = 0x73c0ffff
 BUS_INTERFACE SOPB = opb
 PORT pLED1 = fpga_0_LED1
 PORT pLED2 = fpga_0_LED2
 PORT pLED3 = fpga_0_LED3
END

to the system.mhs file.

Does any see why the LEDs do not change state?

Thanks,
Glenn