Low Dhrystone score on Tricore TC1796

On 20 Jul., 11:11, "Richard (Hitex)" <richa...@tiscali.de> wrote:
> Back to the subject of making sure the code cache is on...  where are
> you linking your code to?  If you link to 0xA....... (e.g. 0xA2000000
> for external SRAM, say) then this isn't cached.  If you link to
> 0x8....... (e.g. 0x82000000) then this accesses it with the cache
> enabled.  Check out page 9-6 of the user manual.  There's no need to
> do this for internal SPRAM (0xd4000000).
Arrgh, so that's the difference between segment 8 and 10... and I've
thought that is generally controlled by the bypass bit CCBYP in
PMI_CON0.
Speed is little more than doubled (32 DMIPs instead of 15 without
cache). Still not anywhere near to 1 DMIPs per MHz, but at least there
is significant improvement. Thanks a lot!

bfroemel@gmail.com wrote:
> On 20 Jul., 11:11, "Richard (Hitex)" <richa...@tiscali.de> wrote:
>> Back to the subject of making sure the code cache is on...  where are
>> you linking your code to?  If you link to 0xA....... (e.g. 0xA2000000
>> for external SRAM, say) then this isn't cached.  If you link to
>> 0x8....... (e.g. 0x82000000) then this accesses it with the cache
>> enabled.  Check out page 9-6 of the user manual.  There's no need to
>> do this for internal SPRAM (0xd4000000).
> Arrgh, so that's the difference between segment 8 and 10... and I've
> thought that is generally controlled by the bypass bit CCBYP in
> PMI_CON0.
> Speed is little more than doubled (32 DMIPs instead of 15 without
> cache). Still not anywhere near to 1 DMIPs per MHz, but at least there
> is significant improvement. Thanks a lot!
> 
You need both: CCBYP turns on caching, and access from 0x8... uses it.
The non-cached address space is mainly used when programming the flash: 
then you must access it directly.