This design uses the open core's I2C master. The core's CPU interface
modified from WISHBONE to AMBA/APB. The latter is done in order to
core and its new APB interface with LEON processor. LEON is written in
therefor the core's VHDL RTL design is tested.
The core also contains a test bench and simulation model for slave,
VERILOG. From the VERILOG test bench only the initialization procedure
is taken and the I2C slave model is translated to VHDL.