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Timer reset on compare match ??

Started by Robert Bielik September 25, 2004
Hi All,

I'm sitting here with a H8S/2633F cpu and I'm setting up a 16 bit TPU
for reset on compare match A (TGRA). The question is: When exactly
will the timer reset ? ON compare match, or the clock pulse after ??

I.e. if I set TGRA to 0x1234, what will the timer range be?
A) 0x0000 - 0x1234 meaning that a loop will contain 0x1235 clock
pulses
B) 0x0000 - 0x1233 -> loop contains 0x1234 clock pulses

I have not seen any clear description to this in the cpu manual.

TIA
/Rob
On 25 Sep, in article
     <33b863b3.0409250155.62f367f3@posting.google.com>
     robert.bielik@gyros.com "Robert Bielik" wrote:
>Hi All, > >I'm sitting here with a H8S/2633F cpu and I'm setting up a 16 bit TPU >for reset on compare match A (TGRA). The question is: When exactly >will the timer reset ? ON compare match, or the clock pulse after ?? > >I.e. if I set TGRA to 0x1234, what will the timer range be? >A) 0x0000 - 0x1234 meaning that a loop will contain 0x1235 clock >pulses
If the counter is reset to zero before counting 0 - 1234 is 1234 pulses to reach 1234... However see later.
>B) 0x0000 - 0x1233 -> loop contains 0x1234 clock pulses
See later
>I have not seen any clear description to this in the cpu manual.
In Rev 4.0 of the PDF that I have the section you need is 11.6 Operation Timing, with particular reference to Figure 11-36 Output Compare Output Timing Figure 11-38 Counter Clear Timing (Compare Match) The COUNTER INPUT clock cycle AFTER the count has stabilised is the time when the compare is done (to allow for full system clock input), and the clear is done HALF a clock cycle later (of SYSTEM CLOCK). So in answer to your question the count interval depends on auto-clearing for periodic or single shot operation. To achieve 0x1234 counts is as follows ASSUMING counter starts at zero:- Mode Compare Value Counts Single 0x1234 0x1234 Periodic 0x1233 0x1233 (first period) 0x1234 (thereafter) The difference on the periodic is that for subsequent repeats one counter input clock cycle is to count to zero. If you need the counter to be periodic and even the first output period needs to be exactly the same as all the ones after, preload the counter with 0xFFFF. In most cases that I have used H8/H8S timers the first period being one pulse less has not been an issue to me. -- Paul Carpenter | paul@pcserviceselectronics.co.uk <http://www.pcserviceselectronics.co.uk/> PC Services <http://www.gnuh8.org.uk/> GNU H8 & mailing list info <http://www.badweb.org.uk/> For those web sites you hate