Forums

FPGA & Softcore Vs FPGA & MCU

Started by ratemonotonic September 11, 2007
Hi all,

I have designed (on paper ) a radio system with the following
components -

1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and
Ethernet controller.
2) A Xilinx FPGA interfaced with the Atmega - responsible for digital
modulation , demodulation of radio signals.
It also interfaces with the Ethernet controller for high bit rate.

the decision behind the ATmega was the low power requirements.

Now I am having second thoughts about this design and am thinking of
FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have
never used a FPGA with CPU core and am not aware of the pros and cons
of it.

I would be grateful if some experienced person could enlighten me
about it.

BR
Rate

"ratemonotonic" <niladri1979@gmail.com> skrev i meddelandet 
news:1189544762.797677.265590@v23g2000prn.googlegroups.com...
> Hi all, > > I have designed (on paper ) a radio system with the following > components - > > 1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and > Ethernet controller. > 2) A Xilinx FPGA interfaced with the Atmega - responsible for digital > modulation , demodulation of radio signals. > It also interfaces with the Ethernet controller for high bit rate. > > the decision behind the ATmega was the low power requirements. > > Now I am having second thoughts about this design and am thinking of > FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have > never used a FPGA with CPU core and am not aware of the pros and cons > of it. > > I would be grateful if some experienced person could enlighten me > about it. > > BR > Rate >
You would be better of with the AT32UC3A0128/256/512 AVR32 which is low power and has an integrated Ethernet MAC. It also has a significant amount of SRAM on board. -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
On Sep 11, 2:06 pm, ratemonotonic <niladri1...@gmail.com> wrote:
> Hi all, > > I have designed (on paper ) a radio system with the following > components - > > 1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and > Ethernet controller. > 2) A Xilinx FPGA interfaced with the Atmega - responsible for digital > modulation , demodulation of radio signals. > It also interfaces with the Ethernet controller for high bit rate. > > the decision behind the ATmega was the low power requirements.
Doesn't sound like you need absolutely lowest power, if you have ethernet anyway.
> > Now I am having second thoughts about this design and am thinking of > FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have > never used a FPGA with CPU core and am not aware of the pros and cons > of it.
I suggest looking into the Actel ProASIC3 with ARM core. $1.5 @250K sound good. Although we wouldn't be buying 250K, it should be reasonable for lower qty. They have ethernet core for the FPGA as well, so you just need the phys.
> > I would be grateful if some experienced person could enlighten me > about it. > > BR > Rate
On Tue, 11 Sep 2007 21:06:02 +0000, ratemonotonic wrote:

> Hi all, > > I have designed (on paper ) a radio system with the following > components - > > 1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and > Ethernet controller. > 2) A Xilinx FPGA interfaced with the Atmega - responsible for digital > modulation , demodulation of radio signals. > It also interfaces with the Ethernet controller for high bit rate. > > the decision behind the ATmega was the low power requirements. > > Now I am having second thoughts about this design and am thinking of > FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have > never used a FPGA with CPU core and am not aware of the pros and cons > of it. > > I would be grateful if some experienced person could enlighten me > about it. > > BR > Rate
No matter what the FPGA vendors tell you, a dedicated processor core is going to take up less silicon per MIP than a soft core. That's how I'd go unless the computational load were small -- and then I'd consider a separate processor as you're doing. Look at your $/MIP with the soft core processor, and $/MIP with a dedicated processor, and use that to guide your decision. -- Tim Wescott Control systems and communications consulting http://www.wescottdesign.com Need to learn how to apply control theory in your embedded system? "Applied Control Theory for Embedded Systems" by Tim Wescott Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html
On Tue, 11 Sep 2007 21:06:02 -0000, ratemonotonic
<niladri1979@gmail.com> wrote in comp.arch.embedded:

> Hi all, > > I have designed (on paper ) a radio system with the following > components - > > 1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and > Ethernet controller. > 2) A Xilinx FPGA interfaced with the Atmega - responsible for digital > modulation , demodulation of radio signals. > It also interfaces with the Ethernet controller for high bit rate. > > the decision behind the ATmega was the low power requirements. > > Now I am having second thoughts about this design and am thinking of > FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have > never used a FPGA with CPU core and am not aware of the pros and cons > of it. > > I would be grateful if some experienced person could enlighten me > about it. > > BR > Rate
linnix already pointed out the Actel FPGA with soft ARM cores. I am actually surprised that this has not come up on this group. Both Xilinx and Altera would love for you to use their soft cores, Microblaze and Nios, respectively. Because the soft core license only allows you to use it on THEIR parts. It's a form of lock-in. If you want to change to a competitor's parts, not only do you need new development tools, but you have to change processor cores, too, meaning extra firmware changes. ARM has announced soft core availability for appropriate parts from Xilinx, Altera, and Actel. Actel gives you the ARM IP license free to use in their parts, because they are the little guy using every advantage they can. Neither Xilinx or Altera even mentions the soft core ARM on their web sites. They don't promote it, or even tell you it exists. Why? Because if you use a soft core ARM instead of Microblaze or Nios, it is that much easier and cheaper to move your design to another manufacturer's parts. -- Jack Klein Home: http://JK-Technology.Com FAQs for comp.lang.c http://c-faq.com/ comp.lang.c++ http://www.parashift.com/c++-faq-lite/ alt.comp.lang.learn.c-c++ http://www.club.cc.cmu.edu/~ajo/docs/FAQ-acllc.html
Ulf Samuelsson wrote:

> "ratemonotonic" <niladri1979@gmail.com> skrev i meddelandet > news:1189544762.797677.265590@v23g2000prn.googlegroups.com... > >>Hi all, >> >>I have designed (on paper ) a radio system with the following >>components - >> >>1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and >>Ethernet controller. >>2) A Xilinx FPGA interfaced with the Atmega - responsible for digital >>modulation , demodulation of radio signals. >>It also interfaces with the Ethernet controller for high bit rate. >> >>the decision behind the ATmega was the low power requirements. >> >>Now I am having second thoughts about this design and am thinking of >>FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have >>never used a FPGA with CPU core and am not aware of the pros and cons >>of it. >> >>I would be grateful if some experienced person could enlighten me >>about it. >> >>BR >>Rate >> > > > You would be better of with the AT32UC3A0128/256/512 AVR32 > which is low power and has an integrated Ethernet MAC. > It also has a significant amount of SRAM on board.
That makes more sense, than Atmega+Ethernet - unless chip-count and cost do not matter to you ? To decide between FPGA + uC, or FPGA+SoftCPU, you do the simple maths, The uC has peripherals - do you need ADC ? If yes, add that as external device to FPGA. The uC has peripherals - do you need UART ? If yes, add that Gate count to FPGA. The uC has FLASH included, and a means to PGM it Add a external FLASH device to your FPGA, or a SRAM, and a larger boot load device. You now have an external memory BUS, so might need more EMC mitigation/more layers. Allow for those costs. The uC has Brownout detect - do you need that ? If yes, add that as external device to FPGA. Add the SoftCPU gate count, and all the peripherals gate counts, and then compare the price delta of the two FPGAs indicated. Add the Config Device Delta, PCB area/layers, assembly costs, etc, and you have your comparisons. Normally, if you can find a std, volume production, uC that WILL do the job, it makes sense to use that. If you HAVE to have external memory on the FPGA anyway, then it is a closer call. -jg
On 12 Sep, 04:40, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Ulf Samuelsson wrote: > > "ratemonotonic" <niladri1...@gmail.com> skrev i meddelandet > >news:1189544762.797677.265590@v23g2000prn.googlegroups.com... > > >>Hi all, > > >>I have designed (on paper ) a radio system with the following > >>components - > > >>1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and > >>Ethernet controller. > >>2) A Xilinx FPGA interfaced with the Atmega - responsible for digital > >>modulation , demodulation of radio signals. > >>It also interfaces with the Ethernet controller for high bit rate. > > >>the decision behind the ATmega was the low power requirements. > > >>Now I am having second thoughts about this design and am thinking of > >>FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have > >>never used a FPGA with CPU core and am not aware of the pros and cons > >>of it. > > >>I would be grateful if some experienced person could enlighten me > >>about it. > > >>BR > >>Rate > > > You would be better of with the AT32UC3A0128/256/512 AVR32 > > which is low power and has an integrated Ethernet MAC. > > It also has a significant amount of SRAM on board. > > That makes more sense, than Atmega+Ethernet - unless chip-count > and cost do not matter to you ? > > To decide between FPGA + uC, or FPGA+SoftCPU, you do the > simple maths, > > The uC has peripherals - do you need ADC ? > If yes, add that as external device to FPGA. > > The uC has peripherals - do you need UART ? > If yes, add that Gate count to FPGA. > > The uC has FLASH included, and a means to PGM it > Add a external FLASH device to your FPGA, or a SRAM, > and a larger boot load device. > > You now have an external memory BUS, so might need > more EMC mitigation/more layers. Allow for those costs. > > The uC has Brownout detect - do you need that ? > If yes, add that as external device to FPGA. > > Add the SoftCPU gate count, and all the peripherals gate > counts, and then compare the price delta of the > two FPGAs indicated. Add the Config Device Delta, > PCB area/layers, assembly costs, etc, > and you have your comparisons. > > Normally, if you can find a std, volume production, uC > that WILL do the job, it makes sense to use that. If you HAVE to have > external memory on the FPGA anyway, then it is a closer call. > > -jg- Hide quoted text - > > - Show quoted text -
Hi Jim , A really helpful suggestion. The only thing thats not clear to me is the 'Config Device Delta' , do you mean the MCU used to boot the bitstream to the FPGA? BR Rate
ratemonotonic wrote:

> > A really helpful suggestion. The only thing thats not clear to me is > the 'Config Device Delta' , do you mean the MCU used to boot the > bitstream to the FPGA?
Sorry a bit brief : - with a typical SoftCPU setup, the config device ( usually a serial Flash device, as they are cheapest ) needs to be larger - to store the CPU itself, and also the code that is then loaded into RAM to run. So, the Config device needs to be larger by two factors, and that will be another cost. -jg
On Sep 12, 1:49 am, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> ratemonotonic wrote: > > > A really helpful suggestion. The only thing thats not clear to me is > > the 'Config Device Delta' , do you mean the MCU used to boot the > > bitstream to the FPGA? > > Sorry a bit brief : - with a typical SoftCPU setup, the config device > ( usually a serial Flash device, as they are cheapest ) needs to be > larger - to store the CPU itself, and also the code > that is then loaded into RAM to run.
ProASIC3 is flash based, so you don't need to store the config bits. However, you do need external program and working memories. You can also build a CF/SD boot loader directly from IP cores.
>>>Hi all, >>> >>>I have designed (on paper ) a radio system with the following >>>components - >>> >>>1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and >>>Ethernet controller. >>>2) A Xilinx FPGA interfaced with the Atmega - responsible for digital >>>modulation , demodulation of radio signals. >>>It also interfaces with the Ethernet controller for high bit rate. >>> >>>the decision behind the ATmega was the low power requirements. >>> >>>Now I am having second thoughts about this design and am thinking of >>>FPGA Devices with Soft / Hardcore and scrapping the ATmega. I have >>>never used a FPGA with CPU core and am not aware of the pros and cons >>>of it. >>> >>>I would be grateful if some experienced person could enlighten me >>>about it. >>> >>>BR >>>Rate >>> >> >> >> You would be better of with the AT32UC3A0128/256/512 AVR32 >> which is low power and has an integrated Ethernet MAC. >> It also has a significant amount of SRAM on board. > > That makes more sense, than Atmega+Ethernet - unless chip-count > and cost do not matter to you ? > > To decide between FPGA + uC, or FPGA+SoftCPU, you do the > simple maths, > > The uC has peripherals - do you need ADC ? > If yes, add that as external device to FPGA. > > The uC has peripherals - do you need UART ? > If yes, add that Gate count to FPGA. > > > The uC has FLASH included, and a means to PGM it > Add a external FLASH device to your FPGA, or a SRAM, > and a larger boot load device. > > You now have an external memory BUS, so might need > more EMC mitigation/more layers. Allow for those costs. > > The uC has Brownout detect - do you need that ? > If yes, add that as external device to FPGA. > > Add the SoftCPU gate count, and all the peripherals gate > counts, and then compare the price delta of the > two FPGAs indicated. Add the Config Device Delta, > PCB area/layers, assembly costs, etc, > and you have your comparisons. > > Normally, if you can find a std, volume production, uC > that WILL do the job, it makes sense to use that. If you HAVE to have > external memory on the FPGA anyway, then it is a closer call. > > -jg >
Another issue is Debugging. Listened to an Actel presentation on Cortex-M1 in FPGA. They can fit a Cortex into a $4 FPGA (large volume), but if you need debugging then the core size increases so much that you need almost 2 x size, so I guess the CPU core is about $8 if you need debugging. -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB