How To Synchronize FPGAs

Hello newsreaders,

For a while I have been confronted with the following task which I find
quite challenging but unfortuantely didn't manage to solve it, yet.
What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one
printed circuit board (PCB). They are used to process a large amount of
incoming serial data (data rates of several GHz's). My idea is to handle
that data parallel by the 2-4 FPGAs. But now there arises the problem how to
adequately split the data and how to synchronize the FPGAs among one
another, in particular?
Is it possible or first of all a realistic idea to synchronize multiple
FPGAs in the GHz range? How can this be done without much protocoll
overhead? I would like to do it without applying an extra transfer protocoll
among the FPGAs just for that purpose! Up to this date I didn't find a
proper solution, yet.
Maybe someone can give me a hint? Any ideas how to solve that problem?

Regards,    Leroy Tanner

Leroy Tanner wrote:
> Hello newsreaders,
> 
> For a while I have been confronted with the following task which I find
> quite challenging but unfortuantely didn't manage to solve it, yet.
> What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one
> printed circuit board (PCB). They are used to process a large amount of
> incoming serial data (data rates of several GHz's). My idea is to handle
> that data parallel by the 2-4 FPGAs. But now there arises the problem how to
> adequately split the data and how to synchronize the FPGAs among one
> another, in particular?
> Is it possible or first of all a realistic idea to synchronize multiple
> FPGAs in the GHz range? How can this be done without much protocoll
> overhead? I would like to do it without applying an extra transfer protocoll
> among the FPGAs just for that purpose! Up to this date I didn't find a
> proper solution, yet.
> Maybe someone can give me a hint? Any ideas how to solve that problem?
> 
> Regards,    Leroy Tanner
> 
> 
Perhaps comp.arch.fpga is a better place to post your question.

Mostafa

-- 
----------------------------------------
Mostafa Kassem
M Dot Kassem At ieee Dot org
---------------------------------------

Leroy Tanner wrote:
> 
... snip ...
> Is it possible or first of all a realistic idea to synchronize
> multiple FPGAs in the GHz range? How can this be done without
> much protocoll overhead? I would like to do it without applying
> an extra transfer protocoll among the FPGAs just for that
> purpose! Up to this date I didn't find a proper solution, yet.

No, it isn't reasonable.  Assuming 'several' means 3, a wire
length of about 2 inches (5 cm) would represent a complete clock
cycle in down and back time, so the devices would have to be
mounted within about 1/10th of that for any hope of reliability. 
Then there is the problem of clock skew, which has similar
limitations.

Thus you are pretty well limited to protocols that expect delay
and handle it, probably by some form of pipeline.

-- 
 "It is not a question of staying the course, but of changing
  the course"                        - John Kerry, 2004-09-20
 "Ask any boat owner the eventual result of continuing the
  present course indefinitely"    - C.B. Falconer, 2004-09-20

Mostafa Kassem <No_one@Nowhere.com> wrote in message news:<_LGdnb9hBKXt-czcRVn-iQ@rogers.com>...
> Leroy Tanner wrote:
> > Hello newsreaders,
> > 
> > For a while I have been confronted with the following task which I find
> > quite challenging but unfortuantely didn't manage to solve it, yet.
> > What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one
> > printed circuit board (PCB). They are used to process a large amount of
> > incoming serial data (data rates of several GHz's). My idea is to handle
> > that data parallel by the 2-4 FPGAs. But now there arises the problem how to
> > adequately split the data and how to synchronize the FPGAs among one
> > another, in particular?

FPGA are parallel in nature internally.  Unless you are maxing out on
the gates, I don't see any advantages in external parallel
processings.  You can alway split functionalities among FPGAs, with a
single serial front-end.  If you are un-powered by a factor of 2 to 4
only, wait a couple of months for a newer and bigger FPGA.

> > Is it possible or first of all a realistic idea to synchronize multiple
> > FPGAs in the GHz range? How can this be done without much protocoll
> > overhead? I would like to do it without applying an extra transfer protocoll
> > among the FPGAs just for that purpose! Up to this date I didn't find a
> > proper solution, yet.
> > Maybe someone can give me a hint? Any ideas how to solve that problem?
> > 
> > Regards,    Leroy Tanner
> > 
> > 
> Perhaps comp.arch.fpga is a better place to post your question.

Yes, but many designers hang out in both places.

> 
> Mostafa

"Linnix" <me@linnix.info-for.us>:

> FPGA are parallel in nature internally.  Unless you are maxing out on
> the gates, I don't see any advantages in external parallel
> processings.  You can alway split functionalities among FPGAs, with a
> single serial front-end.  If you are un-powered by a factor of 2 to 4
> only, wait a couple of months for a newer and bigger FPGA.

It's not a matter of the FPGA fabric but the physically accessible I/Os!
That's why I thought about parallelize some tasks onto several FPGAs..!?

"CBFalconer" <cbfalconer@yahoo.com> :
> No, it isn't reasonable.  Assuming 'several' means 3, a wire
> length of about 2 inches (5 cm) would represent a complete clock
> cycle in down and back time, so the devices would have to be
> mounted within about 1/10th of that for any hope of reliability.
> Then there is the problem of clock skew, which has similar
> limitations.

Hi, thanks for your reply. But what about that calculation? Could you please
elaborate on that? As far as I know I should be (lambda = c/f) ????

Regards,    Leroy

On Fri, 24 Sep 2004 14:05:21 +0200, "Leroy Tanner"
<ikeepthespiritalive@freenet.de> wrote:

>"CBFalconer" <cbfalconer@yahoo.com> :
>> No, it isn't reasonable.  Assuming 'several' means 3, a wire
>> length of about 2 inches (5 cm) would represent a complete clock
>> cycle in down and back time, so the devices would have to be
>> mounted within about 1/10th of that for any hope of reliability.
>> Then there is the problem of clock skew, which has similar
>> limitations.

You could use a proper clock distribution tree built around microstrip
or stripline transmission lines, in which each branch has identical
length. If Wilkinson power dividers are used, the power drops by 3 dB
into each branch and if a constant voltage is needed, the subsequent
sections would have to have a higher impedance.  

>Hi, thanks for your reply. But what about that calculation? Could you please
>elaborate on that? As far as I know I should be (lambda = c/f) ????

In a stripline transmission line on G10 material, the propagation
speed is less than 0.5 c. With teflon board the propagation speed is
closer to c.

A mismatched transmission line longer than about 1/10 wavelength would
mess up the pulse shape. With a mismatched length of 5 cm, the full
wavelength would be 50 cm on G10 and corresponding to more than 1 m
wavelength in free space, which would correspond to a 300 MHz
frequency.

Paul

Leroy Tanner wrote:
> 
> "CBFalconer" <cbfalconer@yahoo.com> :
> > No, it isn't reasonable.  Assuming 'several' means 3, a wire
> > length of about 2 inches (5 cm) would represent a complete clock
> > cycle in down and back time, so the devices would have to be
> > mounted within about 1/10th of that for any hope of reliability.
> > Then there is the problem of clock skew, which has similar
> > limitations.
> 
> Hi, thanks for your reply. But what about that calculation? Could
> you please elaborate on that? As far as I know I should be (lambda
> = c/f) ????

It's very simple.  It takes about 1 nanosec for light to travel 1
foot, or about 25 cm.  Signals on a line (which all signal
propagation is) takes longer.

-- 
 "It is not a question of staying the course, but of changing
  the course"                        - John Kerry, 2004-09-20
 "Ask any boat owner the eventual result of continuing the
  present course indefinitely"    - C.B. Falconer, 2004-09-20

On Wed, 22 Sep 2004 11:16:15 +0200, Leroy Tanner wrote:

> For a while I have been confronted with the following task which I find
> quite challenging but unfortuantely didn't manage to solve it, yet.
> What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one
> printed circuit board (PCB). They are used to process a large amount of
> incoming serial data (data rates of several GHz's). My idea is to handle
> that data parallel by the 2-4 FPGAs. But now there arises the problem how to
> adequately split the data and how to synchronize the FPGAs among one
> another, in particular?

There are two ways to approach this problem:  (1) have each FPGA perform a
part of the process on the entire data stream or (2) have each FPGA
perform the entire process on part of the data stream.  We once
implemented (2) for a bandwidth expander where each chip did the complete
process (one clock cycle Huffman decoding, translation of the code to a
value, then arithmetic processing) for a portion of the incoming data
stream.  Each chip was provided a chunk of the incoming data (e.g., in a
two-chip system, chip one processed chunks 1,3,5,... of the data and
chip two was processed chunks 2,4,6,... of the data).  We actually used two
on the board because of I/O bandwidth limitations, but the chip was
designed to allow for 1,2,4,or 8 chip operation.  


   -=Dave=-

"Paul Keinanen" <keinanen@sci.fi>:

> In a stripline transmission line on G10 material, the propagation
> speed is less than 0.5 c. With teflon board the propagation speed is
> closer to c.
>
> A mismatched transmission line longer than about 1/10 wavelength would
> mess up the pulse shape. With a mismatched length of 5 cm, the full
> wavelength would be 50 cm on G10 and corresponding to more than 1 m
> wavelength in free space, which would correspond to a 300 MHz
> frequency.


Aaah, once again. Unfortunately I didn't get it..!?!

lambda = c / f
c= 300.000 km/s
f = 3 GHz for example, then the wavelength should be

lamba = c / f = 300000/3000000000 = 3/30 = 10 cm!!!

I assume this result is correct by all means. Where does the material come
into play???