JTAG ICE mkII

Hi all ,

I am new to AVRs and am designing circuit for a board. My question for
ppl experienced with AVR and JTAG ICE mkII are -

1) Can JTAG ICE mk II be used for emulation as well as In-Circuit
programming ?

2) Are there any special considerations for circuitry of the target
board to use JTAG ICE mkII for both ISP and Emulation?

BR
Rate

On Sep 27, 6:41 am, ratemonotonic <niladri1...@gmail.com> wrote:

> 1) Can JTAG ICE mk II be used for emulation as well as In-Circuit
> programming ?

Yes, but it's hardly stable.

> 2) Are there any special considerations for circuitry of the target
> board to use JTAG ICE mkII for both ISP and Emulation?

Yes: be prepared for frustration. Wire your board exactly like the
Butterfly. Don't use the multiplexed JTAG I/Os for anything else. Be
prepared for a lot of weird stuff with order of powering things up and
plugging things in. Be prepared to lose contact with the debugger
randomly in the middle of a debug session.

I don't even bother any more. I use an AVRISP mk2 to program the chip
and debug the old-fashioned way, with a scope, LEDs, RS232 etc.

On Sep 27, 5:56 am, larwe <zwsdot...@gmail.com> wrote:
> On Sep 27, 6:41 am, ratemonotonic <niladri1...@gmail.com> wrote:
>
> > 1) Can JTAG ICE mk II be used for emulation as well as In-Circuit
> > programming ?
>
> Yes, but it's hardly stable.

And slow.  It takes forever to step through codes.

>
> > 2) Are there any special considerations for circuitry of the target
> > board to use JTAG ICE mkII for both ISP and Emulation?

Yes, include both interfaces.

>
> Yes: be prepared for frustration. Wire your board exactly like the
> Butterfly. Don't use the multiplexed JTAG I/Os for anything else. Be
> prepared for a lot of weird stuff with order of powering things up and
> plugging things in. Be prepared to lose contact with the debugger
> randomly in the middle of a debug session.
>
> I don't even bother any more. I use an AVRISP mk2 to program the chip
> and debug the old-fashioned way, with a scope, LEDs, RS232 etc.

I use an ARM for ISP programs and JTAG boundary scans.

>I use an ARM for ISP programs and JTAG boundary scans.

Have you written code for ISP commands on the ARM ? or are you using
open source code ? Have you built an ISP?

>Yes, include both interfaces.

I am using  ATMEGA2560 , it has three lines for serial programming -
PDI , PDO and SCK plus the reset , can I use the AVRISP mk2 to
programme it (using the 6 pin header)?  Stupid Question I think , but
worth asking as I dont have any experience on AVRs

Thanks Again

BR
Rate

On Sep 27, 9:20 am, ratemonotonic <niladri1...@gmail.com> wrote:
> >I use an ARM for ISP programs and JTAG boundary scans.
>
> Have you written code for ISP commands on the ARM ? or are you using
> open source code ? Have you built an ISP?
>
> >Yes, include both interfaces.
>
> I am using  ATMEGA2560 , it has three lines for serial programming -
> PDI , PDO and SCK plus the reset ,

Probably the same: MOSI(PDI), MISO(PDO), SCK, RESET, VCC & GND.

> can I use the AVRISP mk2 to
> programme it (using the 6 pin header)?  Stupid Question I think , but
> worth asking as I dont have any experience on AVRs
>
> Thanks Again
>
> BR
> Rate

ratemonotonic wrote:
> 
>> Yes, include both interfaces.

I second that. Put connectors on your board for both ISP and JTAG as 
there are things one can do the other can not.

> I am using  ATMEGA2560 , it has three lines for serial programming -
> PDI , PDO and SCK plus the reset , can I use the AVRISP mk2 to
> programme it (using the 6 pin header)?  Stupid Question I think , but
> worth asking as I dont have any experience on AVRs

The ISP pins are mostly independent of the JTAG pins. You can program 
via JTAG, you can program via ISP. The CPU config flags in EEPROM can 
disable JTAG and then only be reached from ISP. With JTAG enabled they 
can be reached from JTAG but you could screw up and lock yourself out.

IIRC the JTAGICE mkII does not do ISP. The ISP mkII costs all of $35.91, 
cheap enough that you should not skip it when buying a JTAGICE mkII.

As for the 6 pin ISP header, there is an alternate pinout for 10 pins. 
Easier to buy 10 pin cable connectors than 6 if it bothers you to plug a 
10 pin cable into a 6 pin header. Biggest problem in using 10 pins for 
ISP is that the header looks same as a JTAG header to production line 
workers.

The original ISP mkI came with both 6 and 10 pin cables. The 10 pin was 
not a compatible pinout with the 6.

Double check, and triple check, your pinouts for ISP and JTAG as they 
connect to different pins on different AVRs. The ATmega64 tripped me the 
first time as the JTAG documentation named a particular pin function for 
each pin in the header but there was one line 100 or 200 pages into the 
datasheet that said, "Oh by the way the JTAG for this AVR connects to 
these pins rather than those pins used on other AVRs."

Others have mentioned debug sessions on JTAG may run away and require 
your target and JTAG be power cycled in the correct order to recover. 
What I have seen is that this is somehow related to the target board but 
have never figured out why one design works better than others. Happens 
with JTAGICE, JTAGICE mkII, Dragon, and 3rd party JTAG. I have not had 
similar problems using DebugWire. DebugWire is only available on smaller 
parts where JTAG is not available.

On 27 Sep, 18:34, David Kelly <n4...@Yahoo.com> wrote:
> ratemonotonic wrote:
>
> >> Yes, include both interfaces.
>
> I second that. Put connectors on your board for both ISP and JTAG as
> there are things one can do the other can not.
>
> > I am using  ATMEGA2560 , it has three lines for serial programming -
> > PDI , PDO and SCK plus the reset , can I use the AVRISP mk2 to
> > programme it (using the 6 pin header)?  Stupid Question I think , but
> > worth asking as I dont have any experience on AVRs
>
> The ISP pins are mostly independent of the JTAG pins. You can program
> via JTAG, you can program via ISP. The CPU config flags in EEPROM can
> disable JTAG and then only be reached from ISP. With JTAG enabled they
> can be reached from JTAG but you could screw up and lock yourself out.
>
> IIRC the JTAGICE mkII does not do ISP. The ISP mkII costs all of $35.91,
> cheap enough that you should not skip it when buying a JTAGICE mkII.
>
> As for the 6 pin ISP header, there is an alternate pinout for 10 pins.
> Easier to buy 10 pin cable connectors than 6 if it bothers you to plug a
> 10 pin cable into a 6 pin header. Biggest problem in using 10 pins for
> ISP is that the header looks same as a JTAG header to production line
> workers.
>
> The original ISP mkI came with both 6 and 10 pin cables. The 10 pin was
> not a compatible pinout with the 6.
>
> Double check, and triple check, your pinouts for ISP and JTAG as they
> connect to different pins on different AVRs. The ATmega64 tripped me the
> first time as the JTAG documentation named a particular pin function for
> each pin in the header but there was one line 100 or 200 pages into the
> datasheet that said, "Oh by the way the JTAG for this AVR connects to
> these pins rather than those pins used on other AVRs."
>
> Others have mentioned debug sessions on JTAG may run away and require
> your target and JTAG be power cycled in the correct order to recover.
> What I have seen is that this is somehow related to the target board but
> have never figured out why one design works better than others. Happens
> with JTAGICE, JTAGICE mkII, Dragon, and 3rd party JTAG. I have not had
> similar problems using DebugWire. DebugWire is only available on smaller
> parts where JTAG is not available.

Hi all ,
Thanks so much for clearing all this out , I have a much better
understanding of JTAG and ISP from this discussion.
Now I will go and burn the data sheet with my eyes!

Cheers
Rate

David Kelly wrote:
> 
> Others have mentioned debug sessions on JTAG may run away and require 
> your target and JTAG be power cycled in the correct order to recover. 
> What I have seen is that this is somehow related to the target board but 
> have never figured out why one design works better than others. Happens 
> with JTAGICE, JTAGICE mkII, Dragon, and 3rd party JTAG. I have not had 
> similar problems using DebugWire. DebugWire is only available on smaller 
> parts where JTAG is not available.

Updated my Dragon yesterday to AVR Studio 4.13 Service Pack Build 557 
and didn't have the kinds of problems I have had recently with the Dragon.

Wasn't emulating so much as I was only enabling a pin on PORTC and 
toggling its output while playing with the hardware connected. A time or 
two AVR Studio claimed to be changing the output bit, but it didn't 
change on the hardware. Always stuck high if that means anything to anyone.

A power cycle on target and Dragon regained control.

Should point out that static discharges are very likely when fonding 
hardware like this, whether or not I noticed, no matter the precautions. 
System seems to set for hours without problems, only requires power 
cycle reset when I'm poking on it.

On Sep 28, 11:09 am, David Kelly <n4...@Yahoo.com> wrote:

> System seems to set for hours without problems, only requires power
> cycle reset when I'm poking on it.

The real question is: what does it do if locked in a sealed box with a
vial of prussic acid?

On Sep 27, 1:34 pm, David Kelly <n4...@Yahoo.com> wrote:

> IIRC the JTAGICE mkII does not do ISP.

The spec sheet says it can do ISP but doesn't come with an ISP cable.

Eric