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Crossing Clock Domains in CPLD

Started by Unknown October 3, 2007
Hi,

Is there any smart way to pass data thru different clock domains in CPLD 
chips (without internal RAM for fifo) without using additional chips 
like external async fifo ?

I'm using Xilinx's XC95 chips, but I can pick something else.

-- 
voices (at) zrgnyyvpenva (dot) pbz [ROT13]
voices wrote:
> Hi, > > Is there any smart way to pass data thru different clock domains in CPLD > chips (without internal RAM for fifo) without using additional chips > like external async fifo ? > > I'm using Xilinx's XC95 chips, but I can pick something else.
Different clock domains can still be synchroneous, eg when their frequencies are integer multiples. At least one DFF should be between I guess. If the clocks are asynchroneous, two. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
On Oct 3, 2:22 pm, voices <voi...@zrgnyyvpenva.pbz> wrote:
> Hi, > > Is there any smart way to pass data thru different clock domains in CPLD > chips (without internal RAM for fifo) without using additional chips > like external async fifo ? > > I'm using Xilinx's XC95 chips, but I can pick something else.
Whether inside a CPLD or discrete or whatever, you can use a derandomizer, typically 2 D-flipflops in series, clocked by the destination domain clock, with the data clocked by the source domain clock (or completely asynchronous) at the input of the first flipflop. At the output of the second, you have your synchronised data. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------
> > -- > voices (at) zrgnyyvpenva (dot) pbz [ROT13]