Hi, I came across the below statement - "If the oscillator frequency falls below the minimum of a dynamic processor, then that processor may suffer corruption of its registers. " How far is that statement true ? (I have not analysed the Registers in that condition. Did not happen to face that situation ). Regarding the above lines, I think, that when the Osciallator Frequency falls below the minimum of a dynamic processor, then the processor will halt(Stop Functioning)/Idle. So, how is it possible for it to suffer from Register Corruption ? Need clarifications for this. Thx in advans, Karthik Balaguru
Oscillator and Corruption of Registers
Started by ●November 16, 2007
Reply by ●November 16, 20072007-11-16
On Nov 16, 8:02 pm, karthikbalaguru <karthikbalagur...@gmail.com> wrote:> Hi, > I came across the below statement - > "If the oscillator frequency falls below the minimum of a dynamic > processor, then that processor may suffer corruption of its registers. > " > > How far is that statement true ? (I have not analysed the Registers in > that condition. Did not > happen to face that situation ). Regarding the above lines, I think, > that when the Osciallator > Frequency falls below the minimum of a dynamic processor, then the > processor will halt(Stop > Functioning)/Idle. So, how is it possible for it to suffer from > Register Corruption ? Need > clarifications for this. > > Thx in advans, > Karthik BalaguruIn a dynamic processor, the register contents are stored in very small capacitors, very much like DRAM (http://en.wikipedia.org/wiki/ Dynamic_random_access_memory). Unless these registers are refreshed within a certain time, the charges will slowly leak away, and corrupt the data.
Reply by ●November 16, 20072007-11-16
On Nov 17, 12:22 am, Arlet <usene...@c-scape.nl> wrote:> On Nov 16, 8:02 pm, karthikbalaguru <karthikbalagur...@gmail.com> > wrote: > > > > > > > Hi, > > I came across the below statement - > > "If the oscillator frequency falls below the minimum of a dynamic > > processor, then that processor may suffer corruption of its registers. > > " > > > How far is that statement true ? (I have not analysed the Registers in > > that condition. Did not > > happen to face that situation ). Regarding the above lines, I think, > > that when the Osciallator > > Frequency falls below the minimum of a dynamic processor, then the > > processor will halt(Stop > > Functioning)/Idle. So, how is it possible for it to suffer from > > Register Corruption ? Need > > clarifications for this. > > > Thx in advans, > > Karthik Balaguru > > In a dynamic processor, the register contents are stored in very small > capacitors, very much like DRAM (http://en.wikipedia.org/wiki/ > Dynamic_random_access_memory). Unless these registers are refreshed > within a certain time, the charges will slowly leak away, and corrupt > the data.- Hide quoted text - >Your point makes sense if correlated with something like DRAM. But, how does it play a role with a normal processor ? Here Dynamic processor is defined as below (It is a normal Processor with few special features w.r.t Operating Frequency) - 'If the minimum operating frequency of a processor is specified to be greater than zero, then that processor is said to have dynamic operation (Hence called as Dynamic Processor).' Karthik Balaguru
Reply by ●November 16, 20072007-11-16
On Nov 16, 2:34 pm, karthikbalaguru <karthikbalagur...@gmail.com> wrote:> But, how does it play a role with a normal processor ?What part of the statement is ambiguous? In a dynamic processor (ie. one that cannot live if its clock is stopped), the registers are essentially DRAM cells. If they don't get refreshed, they decay. How much margin you have there to under-clock the device depends on the individual chip production variations, temperature, voltage, etc etc.
Reply by ●November 16, 20072007-11-16
On Nov 17, 12:22 am, Arlet <usene...@c-scape.nl> wrote:> On Nov 16, 8:02 pm, karthikbalaguru <karthikbalagur...@gmail.com> > wrote: > > > > > > > Hi, > > I came across the below statement - > > "If the oscillator frequency falls below the minimum of a dynamic > > processor, then that processor may suffer corruption of its registers. > > " > > > How far is that statement true ? (I have not analysed the Registers in > > that condition. Did not > > happen to face that situation ). Regarding the above lines, I think, > > that when the Osciallator > > Frequency falls below the minimum of a dynamic processor, then the > > processor will halt(Stop > > Functioning)/Idle. So, how is it possible for it to suffer from > > Register Corruption ? Need > > clarifications for this. > > > Thx in advans, > > Karthik Balaguru > > In a dynamic processor, the register contents are stored in very small > capacitors, very much like DRAM (http://en.wikipedia.org/wiki/ > Dynamic_random_access_memory). Unless these registers are refreshed > within a certain time, the charges will slowly leak away, and corrupt > the data.-Do you mean to say that the register contents are stored in very small capacitors like DRAM in a Processor ? (DRAM may need to be refreshed thousands of times per second) But, that should making the Processor slow :(:( What do you think ? There are many varities of DRAM . What kind of DRAM can possibly be present inside the processor for storing the register contents ? Any ideas ? Karthik Balaguru
Reply by ●November 16, 20072007-11-16
On Nov 17, 12:36 am, larwe <zwsdot...@gmail.com> wrote:> On Nov 16, 2:34 pm, karthikbalaguru <karthikbalagur...@gmail.com> > wrote: > > > But, how does it play a role with a normal processor ? > > What part of the statement is ambiguous? > > In a dynamic processor (ie. one that cannot live if its clock is > stopped), the registers are essentially DRAM cells. If they don't get > refreshed, they decay. How much margin you have there to under-clock > the device depends on the individual chip production variations, > temperature, voltage, etc etc.Interesting :):) Karthik Balaguru
Reply by ●November 16, 20072007-11-16
On Nov 16, 8:42 pm, karthikbalaguru <karthikbalagur...@gmail.com> wrote:> On Nov 17, 12:22 am, Arlet <usene...@c-scape.nl> wrote: > > > > > On Nov 16, 8:02 pm, karthikbalaguru <karthikbalagur...@gmail.com> > > wrote: > > > > Hi, > > > I came across the below statement - > > > "If the oscillator frequency falls below the minimum of a dynamic > > > processor, then that processor may suffer corruption of its registers. > > > " > > > > How far is that statement true ? (I have not analysed the Registers in > > > that condition. Did not > > > happen to face that situation ). Regarding the above lines, I think, > > > that when the Osciallator > > > Frequency falls below the minimum of a dynamic processor, then the > > > processor will halt(Stop > > > Functioning)/Idle. So, how is it possible for it to suffer from > > > Register Corruption ? Need > > > clarifications for this. > > > > Thx in advans, > > > Karthik Balaguru > > > In a dynamic processor, the register contents are stored in very small > > capacitors, very much like DRAM (http://en.wikipedia.org/wiki/ > > Dynamic_random_access_memory). Unless these registers are refreshed > > within a certain time, the charges will slowly leak away, and corrupt > > the data.- > > Do you mean to say that the register contents are stored in > very small capacitors like DRAM in a Processor ? > (DRAM may need to be refreshed thousands of times per second) > But, that should making the Processor slow :(:( > What do you think ?It doesn't necessarily make the processor slow. It just requires special consideration in the implementation. As long as registers are updated during the normal flow of instructions, they will be automatically refreshed every cycle or every couple of cycles. For registers that need to keep the same contents, you just add an extra path from the register back to itself, so that the old contents will be written again.> > There are many varities of DRAM . What kind of DRAM can > possibly be present inside the processor for storing the register > contents ? Any ideas ?The many varieties of DRAM are mostly with regards to the external interface. The internal design of the single DRAM cell does not vary much. It's basically a single transistor and some capacitance.
Reply by ●November 16, 20072007-11-16
larwe wrote:> In a dynamic processor (ie. one that cannot live if its clock is > stopped), the registers are essentially DRAM cells.There were two typical architectures for that purpose: two phase and four phase. The last dynamic CPU probably was the original i8080. Since then all general purpose CPU designs were static.> If they don't get > refreshed, they decay. How much margin you have there to under-clock > the device depends on the individual chip production variations, > temperature, voltage, etc etc.The underclocking margin on the modern CPUs is governed by the operational limits of the internal PLL. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●November 16, 20072007-11-16
"karthikbalaguru" <karthikbalaguru79@gmail.com> wrote in message news:6a3a1a12-3b8a-4fd5-95ec-ae0524e800bd@f13g2000hsa.googlegroups.com...> Hi, > I came across the below statement - > "If the oscillator frequency falls below the minimum of a dynamic > processor, then that processor may suffer corruption of its registers. > " > > How far is that statement true ? (I have not analysed the Registers in > that condition. Did not > happen to face that situation ). Regarding the above lines, I think, > that when the Osciallator > Frequency falls below the minimum of a dynamic processor, then the > processor will halt(Stop > Functioning)/Idle. So, how is it possible for it to suffer from > Register Corruption ? Need > clarifications for this.The registers are made of a type of memory that needs to be refreshed periodically. That is true of a dynamic processor. A static processor works the way you describe.
Reply by ●November 16, 20072007-11-16
Vladimir Vassilevsky wrote:> larwe wrote: > >> In a dynamic processor (ie. one that cannot live if its clock is >> stopped), the registers are essentially DRAM cells. > > There were two typical architectures for that purpose: two phase and > four phase. > > The last dynamic CPU probably was the original i8080. Since then all > general purpose CPU designs were static.IIRC the 8080 (and z80) was static. It could be halted without harm. -- Chuck F (cbfalconer at maineline dot net) <http://cbfalconer.home.att.net> Try the download section. -- Posted via a free Usenet account from http://www.teranews.com
