I2C trick?

  Suppose you have the two I2C slaves that have to be connected to the 
MCU. Both slaves have the same I2C address. The I2C master is simulated 
by bit banging.

Would it be possible to swap SCL and SDA lines on one of the slaves so 
both slaves can be addressed independently? Can this cause any "side 
effects" ?



Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Vladimir Vassilevsky wrote:

>  Suppose you have the two I2C slaves that have to be connected to the 
>MCU. Both slaves have the same I2C address.

First time I hear somebody doing this. Even if the devices are
"write-only" this is bad design.  For example, how to diagnose
communication problems with one of them?

>The I2C master is simulated 
>by bit banging.
>
>Would it be possible to swap SCL and SDA lines on one of the slaves so 
>both slaves can be addressed independently?

No.  The SDA line must be stable while SCL is high, unless when
violating this rule on purpose to signal START or STOP conditions.
(SDA going low or SDA going high while clock is high, respectively)
You could not keep the phase relationships correct with arbitrary data
patterns.

> Can this cause any "side >effects" ?

Anything from just not working to a total bus lockup, (if devices
detect a START but not a STOP.)

If you can not configure one I2C slave to a different address or
provide another port, consider adding I2C multiplexers or switches to
the bus (PCA9545, for example)


Roberto Waltman

[ Please reply to the group,
  return address is invalid ]

Roberto Waltman wrote:

>> Suppose you have the two I2C slaves that have to be connected to the 
>>MCU. Both slaves have the same I2C address.
> 
> 
> First time I hear somebody doing this. Even if the devices are
> "write-only" this is bad design.  For example, how to diagnose
> communication problems with one of them?

Of course the slaves should be addressed independently. The I2C address 
can't be changed for those ICs, and there are only two I/O pins 
available on the MCU. Would it be possible to get by without some sort 
of I/O extender?


>>Would it be possible to swap SCL and SDA lines on one of the slaves so 
>>both slaves can be addressed independently?
>  
> No.  The SDA line must be stable while SCL is high, unless when
> violating this rule on purpose to signal START or STOP conditions.

Understood. But how exactly this can disrupt the communication?
Yes, the multiple wrong starts and stops could be detected. So?

> Anything from just not working to a total bus lockup, (if devices
> detect a START but not a STOP.)

Would you describe a scenario which can lead to an unrecoverable problem?

> If you can not configure one I2C slave to a different address or
> provide another port, consider adding I2C multiplexers or switches to
> the bus (PCA9545, for example)

Well you don't have to reprint the basic stuff from an ABC book on 
electronics.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

On Dec 28, 11:27=A0am, Vladimir Vassilevsky <antispam_bo...@hotmail.com>
wrote:

> > Anything from just not working to a total bus lockup, (if devices
> > detect a START but not a STOP.)
>
> Would you describe a scenario which can lead to an unrecoverable problem?

If both slaves go on-bus in output mode then both SCL and SDA lines
are being driven hard by the slaves; how is the master going to create
edges?

I can imagine you could do very funky things with voltage dividers to
ensure that the master could always assert its will over both I/Os
regardless of what the other end is trying to do, but this would
result in some horrible non-spec I2C implementation. I can't imagine
shipping such a hack.

Vladimir Vassilevsky <antispam_bogus@hotmail.com> wrote:
> 
> 
> Roberto Waltman wrote:
> 
>>> Suppose you have the two I2C slaves that have to be connected to the 
>>>MCU. Both slaves have the same I2C address.
>> 
>> First time I hear somebody doing this. Even if the devices are
>> "write-only" this is bad design.  For example, how to diagnose
>> communication problems with one of them?
> 
> Of course the slaves should be addressed independently. The I2C address 
> can't be changed for those ICs, and there are only two I/O pins 
> available on the MCU. Would it be possible to get by without some sort 
> of I/O extender?

If you don't care for standards and specs, you could just wire things up
as you described and see if it works for your setup and your chips. No
guarantee it will work in all situations of course, even if your tests
happen to work.

>> No.  The SDA line must be stable while SCL is high, unless when
>> violating this rule on purpose to signal START or STOP conditions.
> 
> Understood. But how exactly this can disrupt the communication?
> Yes, the multiple wrong starts and stops could be detected. So?

The behaviour of an I2C chip is only defined as long as the signals on
the bus stick to the protocol. If the protocol is violated, just about
anything could happen, including a device locking up the bus forever.
This might happen right away, or after a few seconds, or after a few
days. If you're really unlucky, it happens only every few months.

What you are proposing is called 'undefined behaviour'. Anything could
happen, but no way to predict what or when.

>> If you can not configure one I2C slave to a different address or
>> provide another port, consider adding I2C multiplexers or switches to
>> the bus (PCA9545, for example)
> 
> Well you don't have to reprint the basic stuff from an ABC book on 
> electronics.

Sorry to interfere, but I think there is no reason to snap at somebody
who is taking the time to anwer your questions if his answer is not what
you want to hear.  I think the only answer you'll get is the one you
already got: violating the protocol is just not a good idea - that's
what protocols are for. Do what you please, but don't be surprised if
things will not work out the way you planned.

-- 
:wq
^X^Cy^K^X^C^C^C^C

"larwe" <zwsdotcom@gmail.com> wrote in message
news:5980266c-d5ab-42e2-8cd5-609ba19d84f9@f52g2000hsa.googlegroups.com...
On Dec 28, 11:27 am, Vladimir Vassilevsky <antispam_bo...@hotmail.com>
wrote:

> > Anything from just not working to a total bus lockup, (if devices
> > detect a START but not a STOP.)
>
> Would you describe a scenario which can lead to an unrecoverable problem?

>If both slaves go on-bus in output mode then both SCL and SDA lines
>are being driven hard by the slaves; how is the master going to create
>edges?

Hi Larwe,

Thank you for the meaningful response.
The I2C bus is supposed to ignore the incorrect sequences on the bus;  so I
don't see a problem there. What you mentioned is possible only if the
hardware is broken.


>I can imagine you could do very funky things with voltage dividers to
>ensure that the master could always assert its will over both I/Os
>regardless of what the other end is trying to do, but this would
>result in some horrible non-spec I2C implementation. I can't imagine
>shipping such a hack.

There should not be a need for such complication. So far nobody suggested a
valid reason why exactly it is a bad idea to swap the SCL and SDA to
separate the I2C slaves. I tried to do that; everything worked like
expected. This could actually be a good trick.

VLV

Vladimir Vassilevsky wrote:
> "larwe" <zwsdotcom@gmail.com> wrote in message
>>I can imagine you could do very funky things with voltage dividers to
>>ensure that the master could always assert its will over both I/Os
>>regardless of what the other end is trying to do, but this would
>>result in some horrible non-spec I2C implementation. I can't imagine
>>shipping such a hack.
> 
> There should not be a need for such complication. So far nobody suggested a
> valid reason why exactly it is a bad idea to swap the SCL and SDA to
> separate the I2C slaves. I tried to do that; everything worked like
> expected. This could actually be a good trick.

This trick is on the same level as assuming things about freshly-
malloced memory or relations between the addresses of local variables in
a program C. It may work, but it's not guaranteed.

If I see that correctly, the line-swapped device will see a start
condition whenever the master sends a '1' bit followed by a '0'; it will
see a '0' bit during a direction swap (between master releasing SDA
after the last bit and slave pulling SDA for acknowledge), and a '1' bit
during inactive periods (between a stop condition and a start
condition). This means, it is possible to construct a valid transaction
that is seen as, say, a start condition plus 8 data bits by the
line-swapped device. That device may now start pulling its SDA (i.e. the
current SCL) to low as an acknowledge, and thus lock up the bus.

Sure it's unlikely. But I've already seen devices lock up I2C even when
doing protocol, so I would avoid that trick if I can. Who knows what
goofs lurk in this world's I2C implementations.


  Stefan

"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message 
news:ls8dj.869$pA7.425@newssvr25.news.prodigy.net...
>
>  Suppose you have the two I2C slaves that have to be connected to the MCU. 
> Both slaves have the same I2C address. The I2C master is simulated by bit 
> banging.
>
<snip>

If you MUST have 2   i2c devices with the same address then NXP have some 
address extender IC's.

Joe

On Sun, 30 Dec 2007 15:52:56 +1100, "Joe G \(Home\)"
<joe.g@optusnet.com.au> wrote:

>"Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message 
>news:ls8dj.869$pA7.425@newssvr25.news.prodigy.net...
>>
>>  Suppose you have the two I2C slaves that have to be connected to the MCU. 
>> Both slaves have the same I2C address. The I2C master is simulated by bit 
>> banging.
>>
><snip>
>
>If you MUST have 2   i2c devices with the same address then NXP have some 
>address extender IC's.

They also have the PCA9540B 2-channel I2C multiplexer.  Simple.  Safe.

-- 
Dan Henry

"Stefan Reuther" <stefan.news@arcor.de> wrote in message
news:fl655s.mk.1@stefan.msgid.phost.de...
> Vladimir Vassilevsky wrote:

> > So far nobody suggested a
> > valid reason why exactly it is a bad idea to swap the SCL and SDA to
> > separate the I2C slaves.

> If I see that correctly, the line-swapped device will see a start
> condition whenever the master sends a '1' bit followed by a '0'; it will
> see a '0' bit during a direction swap (between master releasing SDA
> after the last bit and slave pulling SDA for acknowledge), and a '1' bit
> during inactive periods (between a stop condition and a start
> condition). This means, it is possible to construct a valid transaction
> that is seen as, say, a start condition plus 8 data bits by the
> line-swapped device. That device may now start pulling its SDA (i.e. the
> current SCL) to low as an acknowledge, and thus lock up the bus.

I thought for a little about what you suggested, still I can't see how this
is possible. Would you please give an example.

> Sure it's unlikely. But I've already seen devices lock up I2C even when
> doing protocol, so I would avoid that trick if I can. Who knows what
> goofs lurk in this world's I2C implementations.

This is certainly true.  However I emphasise that nothing in the I2C
standard precludes from doing the tricks like that. There are no unfounded
assumptions. Everything behaves exactly as described.

Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com