Can an RTOS guarantee that interrupt latency will never exceed a predefined maximum?

Do we need to configure Interrupt rate limiting on the processor per
application basis? If so, can I configure it on only selective
interrupts?

NewToFPGA wrote:
> Do we need to configure Interrupt rate limiting on the processor per
> application basis? If so, can I configure it on only selective
> interrupts?

If a device supports it properly, it can be always be enabled. If the 
amount of traffic is low, the device won't delay the interrupts (low 
latency/bandwidth). Only if  the interrupt rate is going up, and there 
is still FIFO space available, the interrupt rate will be limited, which 
trades off higher latency for higher bandwidth.

Consult the documentation of any devices capable of interrupt rate 
limiting for exact details of this option.

NewToFPGA wrote:
> Can an RTOS guarantee that interrupt latency will never exceed a
> predefined maximum? if so, where do we define this value in the
> programming?

No. But, It can be done by careful design of your system by you.

Karthik Balaguru