Wishbone, TSK3000 and endianness problem

Started by argee April 16, 2008
Hi all,

I'm working on interfacing a custom IP core to a TSK3000 (Altium's
P/H:MIPS-like soft processor) over WISHBONE bus and it seems I've run
into some endianness problems. I've always been confused by endianness
issues and now, after a few days of debugging both hardware and
software, my head is ready to explode.

The TSK3000's datasheet states that the processor uses only BIG endian
byte ordering, so I started from that. After I created the interface for
my core, connected it through Altium's "Configurable Wishbone
Interconnect" and started running test apps, I observed a strange
behavior which led me to further debugging and eventually to hooking up
a logical analyzer to the bus. I've hardcoded WISHBONE SLAVE DAT_O(31
downto 0) to 0x44332211 and have tried different pointer games with the
design and this is what bothers me:

When I read form the interface using uint32_t *, I get the same
hardcoded data (0x44332211). The WISHBONE specification states that the
byte ordering for 32-bit BIG endian ports with byte granularity is...
well.. big-endianny. I.e. BYTE(0) of a 32-bit word should be the one at
DAT_O(31 downto 24), and BYTE(3) should be at DAT_O(7 downto 0). So I
expect that my C variable should be 0x11223344 (?). This behavior seems
a bit little-endiany to me... On the other hand, when I access the
interface though uint8_t *, only SEL_I(3) is active and 0x44 is read
which is the correct big endian BYTE(0).

What am I doing/thinking wrong? *nisc_ctrl_8Any help/ideas would be 
greatly appreciated!