Forums

Driving tri-state LED matrix

Started by Unknown May 30, 2008
The objective is as follows:
    uC pin set as output high:  The Green LED lights up
    uC pin set as output low:   The Red LED lights up
    uC pin set as input:           Both LED's are off

There will never be a time when both LED's are lit.

Here's what I'm currently thinking of for the circuit:



As you can see, I've marked the current path from Vcc, thru a PNP
transistor, thru an NPN transistor, to ground. As far as I'm aware,
this current path will be problematic in that it will in theory keep
both transistors always turned on. What I'm puzzled about, however, is
that I used this exact same setup for my college project and it worked
perfectly... but I don't see how both transistors weren't always
turned on. There will be 700 mV dropped across each BE junction,
granted, but then that still leaves 3.6 V to be dropped across bare
metal... so I thought there should have been a high enough current for
both transistors to be turned on?? I used BC337's and BC327's for my
project.

On May 30, 1:18=A0pm, Tom=E1s =D3 h=C9ilidhe <t...@lavabit.com> wrote:

> Here's what I'm currently thinking of for the circuit:
My link disappeared for some reason. Here it is: http://users.imagine.ie/toe/disp.jpg
On 2008-05-30, Tom&#2013265921;s &#2013265939; h&#2013265929;ilidhe <toe@lavabit.com> wrote:
> On May 30, 1:18&#2013266080;pm, Tom&#2013265921;s &#2013265939; h&#2013265929;ilidhe <t...@lavabit.com> wrote: > >> Here's what I'm currently thinking of for the circuit: > > My link disappeared for some reason. Here it is: > > http://users.imagine.ie/toe/disp.jpg
Try redrawing this in a conventional manner, with Vcc at the top. I started looking at this diagram but I lost interest the minute I saw that I was going to have to unravel the circuit before considering it. There's only so much time people are willing to invest in considering a news post. -- Andrew Smallshaw andrews@sdf.lonestar.org
On May 30, 3:06=A0pm, Andrew Smallshaw <andr...@sdf.lonestar.org> wrote:

> Try redrawing this in a conventional manner, with Vcc at the top. > I started looking at this diagram but I lost interest the minute > I saw that I was going to have to unravel the circuit before > considering it. =A0There's only so much time people are willing to > invest in considering a news post.
Are you talking about the way the emitter on the PNP is the bottom pin rather than the top pin? If so: http://users.imagine.ie/toe/disp2.jpg
"Tom&#2013265921;s &#2013265939; h&#2013265929;ilidhe" <toe@lavabit.com> wrote in message 
news:b0519651-362b-48ae-ac6d-fa93f7a3b3b8@59g2000hsb.googlegroups.com...
On May 30, 3:06 pm, Andrew Smallshaw <andr...@sdf.lonestar.org> wrote:

> Try redrawing this in a conventional manner, with Vcc at the top. > I started looking at this diagram but I lost interest the minute > I saw that I was going to have to unravel the circuit before > considering it. There's only so much time people are willing to > invest in considering a news post.
Are you talking about the way the emitter on the PNP is the bottom pin rather than the top pin? If so: http://users.imagine.ie/toe/disp2.jpg Tomas - There is a reason for transistor symbols looking a bit like a diode between the base and emitter. In your circuit a big current will flow from VCC through the emitter and out of the base of the first (leftmost) PNP transistor, into the base and out of the emitter of the NPN transistor. The second PNP transistor will turn on, the first two transistors will be destroyed. Why not download SwitcheCAD from www.linear.com and simulate your ciruits. Michael Kellett www.mkesc.co.uk
On May 30, 3:53=A0pm, "MK" <nos...@please.com> wrote:

> In your circuit a big current will flow from VCC > through the emitter and out of the base of the first (leftmost) PNP > transistor, into the base and out of the emitter of the NPN transistor. Th=
e
> second PNP transistor will turn on, the first two transistors will be > destroyed.
See this is exactly what I was thinking... but miraculously this worked perfectly in my college project. Even if my board mixed up the collector with the emitter for one of the transistors, it still doesn't explain why both transistors weren't always turned on... ?!
Tom&#2013265921;s &#2013265939; h&#2013265929;ilidhe wrote:
> "MK" <nos...@please.com> wrote: > >> In your circuit a big current will flow from VCC through the >> emitter and out of the base of the first (leftmost) PNP >> transistor, into the base and out of the emitter of the NPN >> transistor. The second PNP transistor will turn on, the first >> two transistors will be destroyed. > > See this is exactly what I was thinking... but miraculously this > worked perfectly in my college project. Even if my board mixed up > the collector with the emitter for one of the transistors, it still > doesn't explain why both transistors weren't always turned on... ?!
Transistors work with emitter/collector exchanged. Their efficiency, Vcc, etc. are sharply curtailed. They are not characterized for such operation. -- [mail]: Chuck F (cbfalconer at maineline dot net) [page]: <http://cbfalconer.home.att.net> Try the download section. ** Posted from http://www.teranews.com **
On May 30, 4:53=A0pm, CBFalconer <cbfalco...@yahoo.com> wrote:

> > See this is exactly what I was thinking... but miraculously this > > worked perfectly in my college project. Even if my board mixed up > > the collector with the emitter for one of the transistors, it still > > doesn't explain why both transistors weren't always turned on... ?! > > Transistors work with emitter/collector exchanged. =A0Their > efficiency, Vcc, etc. are sharply curtailed. =A0They are not > characterized for such operation.
Is there anyway I can get this to work... ? I'm thinking of using one BJT and one FET, and also a pull-up/down resistor. I'll make up a circuit and post a picture.
On May 30, 7:42=A0pm, Tom=E1s =D3 h=C9ilidhe <t...@lavabit.com> wrote:

> Is there anyway I can get this to work... ? I'm thinking of using one > BJT and one FET, and also a pull-up/down resistor. I'll make up a > circuit and post a picture.
OK here's what I've got: http://users.imagine.ie/toe/disp3.JPG A few points about it: * Because the source of the NMOS isn't going directly to ground, I have to get a FET that has a 4th pin for the bulk. * The 10k is a suitable resistor value to put the transistor into saturation. * The 200k is a pull-down resistor to ensure that the NMOS gate is kept low when the uC pin is set to high-impedence. This resistor should be as high as possible to ensure that it doesn't provide a current path that will turn on the PNP transistor all the time, but at the same time it has to be significantly smaller than the output resistance of the uC pin to ensure that the entire 5 V is dropped within uC, leaving close enough to 0 V across the 200k resistor. Any thoughts? (..other than the repetitive "get yourself a uC with more pins")
Tom&#2013265921;s &#2013265939; h&#2013265929;ilidhe wrote:
> Any thoughts? (..other than the repetitive "get yourself a uC with > more pins")
I have already suggested the MOSFET drivers that preserve the 3 State Pin sense. Many now do this, to allow lower idle powers in SMPS. Much lower parts count, and no gymnastics. -jg