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ARM9 STR912 IRQ woes (GCC/Eclipse/OpenOCD)

Started by frikkiethirion June 2, 2008
Hi ppl,

I've been playing with GCC (4.3) (newlib)/Eclipse/OpenOCD to try and get
a
timer interupt working. I've managed to see in the VIC0 interrupt
status registers that the interrupt flag for timer0 is set on a "TOF"
(timer overflow) of the timer. 

The problem is that the CPU doesn't branch to execute my interrupt service
routine. Placing a breakpoint in the startup code at 'LDR PC, [PC,
#-0x0FF0] doesn't get hit at all.

Can anybody please give me some pointers on what else to look at to
determine why the interrupt isn't executed?

Regards,
-Frikkie Thirion


//Startup code snippet:
Vectors:
        LDR     PC, Reset_Addr      /* 0x0000 */        
        LDR     PC, Undef_Addr      /* 0x0004 */        
        LDR     PC, SWI_Addr     /* 0x0008 */        
        LDR     PC, PAbt_Addr       /* 0x000C */        
        LDR     PC, DAbt_Addr       /* 0x0010 */        
        NOP                   /* 0x0014 Reserved Vector */
      LDR     PC, [PC, #-0x0FF0] /* Vector from VicVECAddr */     
        LDR     PC, FIQ_Addr     /* 0x001C FIQ has no vector!  */

Reset_Addr:     .word   Hard_Reset
Undef_Addr:     .word   Undef_Handler
SWI_Addr:       .word   SWI_Handler
PAbt_Addr:      .word   PAbt_Handler
DAbt_Addr:      .word   DAbt_Handler
                .word   0                      /* Reserved Address */
IRQ_Addr:       .word   IRQ_Handler
FIQ_Addr:       .word   FIQ_Handler

Undef_Handler:  B       Undef_Handler
SWI_Handler:    B       SWI_Handler
PAbt_Handler:   B       PAbt_Handler
DAbt_Handler:   B       DAbt_Handler
IRQ_Handler:   B     IRQ_Handler       /* should never get here ... */
FIQ_Handler:    B       FIQ_Handler


In main():
----------
HAL_isr_init();
HAL_isr_init_timer0();

//What is the contents of the interrupt service routine?
wI=VIC0->VICx_ISR;    
if ( (wI&0x10) == 0x10)
{
   wI=0;  // Place to put a breakpoint - (This gets hit in GDB)
}


HAL_isr_init():
---------------
u32 wI;
//Enable SCU clock to peripheral:
//Set bit[5] in SCU Peripheral Clock Gating Register 0
wI = SCU->PCGR0;
wI |= 0x00000020; //[5] = VIC
SCU->PCGR0=wI;

//Take peripheral out or reset:
//Set bit[5] in SCU Peripheral Reset Register 0
wI = SCU->PRR0;
wI |= 0x00000020; //[5] = VIC
SCU->PRR0=wI;
     
//Assign a default function routine to the DVAR, for spurious
//interrupts
VIC0->VICx_DVAR=(u32)HAL_isr_default_VIC0_isr;
VIC1->VICx_DVAR=(u32)HAL_isr_default_VIC1_isr;    


HAL_isr_init_timer0()
---------------------
// Interrupt enable: VICx_inter, p118
wI=VIC0->VICx_INTER;
wI|=(1<<4);  // VIC0.4 = timer0
VIC0->VICx_INTER=wI;

// Interrupt select register, p118
wI= VIC0->VICx_INTSR;
wI&=~(1<<4);     // Set [4] to 0.
VIC0->VICx_INTSR=wI;

// Vector address i registers
// Set 'vector address' to Timer0's ISR
VIC0->VICx_VA4R=(u32)&HAL_TIM0_isr; 

// Vector control i registers, p122
wI=4;  //[3..0] = These bits select the interrupt source for the 
         //vectored interrupt.
wI|=(1<<5);   //[5]   = Enable
VIC0->VICx_VC4R=wI; // Select VICx_VC4R to match VIC0.4 for timer0




> I've been playing with GCC (4.3) (newlib)/Eclipse/OpenOCD to try and get > a > timer interupt working. I've managed to see in the VIC0 interrupt > status registers that the interrupt flag for timer0 is set on a "TOF" > (timer overflow) of the timer. > > The problem is that the CPU doesn't branch to execute my interrupt service > routine. Placing a breakpoint in the startup code at 'LDR PC, [PC, > #-0x0FF0] doesn't get hit at all. > > Can anybody please give me some pointers on what else to look at to > determine why the interrupt isn't executed? > > Regards, > -Frikkie Thirion >
Sorry if this is a statement of the obvious, but have you checked that the I bit in the status register is set such that interrupt are globally enabled? -- Regards, Richard. + http://www.FreeRTOS.org & http://www.FreeRTOS.org/shop 17 official architecture ports, more than 5000 downloads per month. + http://www.SafeRTOS.com Certified by T&#2013265948;V as meeting the requirements for safety related systems.
Hi Richard

>Sorry if this is a statement of the obvious, but have you checked that
the
>I bit in the status register is set such that interrupt are globally >enabled?
I've double checked my startup assembly again and found in the section where the stacks are defined that no mention is made about the user mode! (never copy and paste example code...). I've added the following at the bottom of the stack initialization and now everything works ;) # Set up User Mode and set User Mode Stack msr CPSR_c, #Mode_USR mov r13, r0 sub r0, r0, #USR_Stack_Size Thank you for replying to my post. I was going a bit postal trying to figure out what was going on. Now I can enjoy a quiet evening watching my status LEDs flash to the tune of my timer interrupt ;) Regards, -frikkie