Forums

Debugging Embedded Dram - Need Help

Started by Jim Flanagan June 21, 2008
Hi -
I'm attempting to debug a problem with an existing embedded controller 
board.  The board uses a MC68020 and uses either 1 or 2 banks of 30pin
simm memory.  I think this is a 199? design.  The board supports either
1M or 4M memory.  The SIMM memory is configured to be accessed as a 
16bit wide data bus.  The 1M memory works OK, but there are read/write 
errors when using the 4M memory.  I'm confident the 4M memory that I 
bought is compatible, as I've studied the datasheets for both 1 and 4M 
and their topologies and access speeds are the same.  No parity is used 
in this design.  Refresh (<15uSec CBR time) and access times (70nSec) 
are the same and I've looked at the ras/cas  timing and compared them 
against the datasheet and they look like there is plenty of timing margin.

What would you guys suggest as to how and troubleshoot this problem?

The 4M is brand new, quality memory and the timing looks good.  Where
would my problem possibly lie?  I have not looked yet at signal 
integrity (signal ringing, etc). I've also not looked at any  potential 
power supply problems either.  I've noticed on the schematics that there
are no termination resistors, but I figured that this is a fairly slow 
bus and since the 1M memory is not having any issues, that this would 
not likely be an issue.

Anyway, if you can offer any tips on testing the signal integrity or any
other ideas, it would be appreciated.

Thanks.
Jim
On Sat, 21 Jun 2008 20:54:06 -0400, the renowned Jim Flanagan
<jflan@tampaREMOVEbay.rr.com> wrote:

> >Hi - >I'm attempting to debug a problem with an existing embedded controller >board. The board uses a MC68020 and uses either 1 or 2 banks of 30pin >simm memory. I think this is a 199? design. The board supports either >1M or 4M memory. The SIMM memory is configured to be accessed as a >16bit wide data bus. The 1M memory works OK, but there are read/write >errors when using the 4M memory. I'm confident the 4M memory that I >bought is compatible, as I've studied the datasheets for both 1 and 4M >and their topologies and access speeds are the same. No parity is used >in this design. Refresh (<15uSec CBR time) and access times (70nSec) >are the same and I've looked at the ras/cas timing and compared them >against the datasheet and they look like there is plenty of timing margin. > >What would you guys suggest as to how and troubleshoot this problem? > >The 4M is brand new, quality memory and the timing looks good. Where >would my problem possibly lie? I have not looked yet at signal >integrity (signal ringing, etc). I've also not looked at any potential >power supply problems either. I've noticed on the schematics that there >are no termination resistors, but I figured that this is a fairly slow >bus and since the 1M memory is not having any issues, that this would >not likely be an issue. > >Anyway, if you can offer any tips on testing the signal integrity or any >other ideas, it would be appreciated. > >Thanks. >Jim
Could the refresh counter be too narrow? Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
Spehro Pefhany wrote:
> On Sat, 21 Jun 2008 20:54:06 -0400, the renowned Jim Flanagan > <jflan@tampaREMOVEbay.rr.com> wrote: > >> Hi - >> I'm attempting to debug a problem with an existing embedded controller >> board. The board uses a MC68020 and uses either 1 or 2 banks of 30pin >> simm memory. I think this is a 199? design. The board supports either >> 1M or 4M memory. The SIMM memory is configured to be accessed as a >> 16bit wide data bus. The 1M memory works OK, but there are read/write >> errors when using the 4M memory. I'm confident the 4M memory that I >> bought is compatible, as I've studied the datasheets for both 1 and 4M >> and their topologies and access speeds are the same. No parity is used >> in this design. Refresh (<15uSec CBR time) and access times (70nSec) >> are the same and I've looked at the ras/cas timing and compared them >> against the datasheet and they look like there is plenty of timing margin. >> >> What would you guys suggest as to how and troubleshoot this problem? >> >> The 4M is brand new, quality memory and the timing looks good. Where >> would my problem possibly lie? I have not looked yet at signal >> integrity (signal ringing, etc). I've also not looked at any potential >> power supply problems either. I've noticed on the schematics that there >> are no termination resistors, but I figured that this is a fairly slow >> bus and since the 1M memory is not having any issues, that this would >> not likely be an issue. >> >> Anyway, if you can offer any tips on testing the signal integrity or any >> other ideas, it would be appreciated. >> >> Thanks. >> Jim > > Could the refresh counter be too narrow? > > > Best regards, > Spehro Pefhany
I'm sorry, I don't understand what you mean by 'too narrow'? According to the 4M datasheet, using CBR should take no more than 64mSec or 15uSec per column, assuming a square matrix (2^11). I see the refresh counter performing a refresh cycle about every 12uSec. So, I should be OK, or am I missing something? Thanks for the input. Jim
On Sat, 21 Jun 2008 21:22:52 -0400, Jim Flanagan
<jflan@tampaREMOVEbay.rr.com> wrote:

> >Spehro Pefhany wrote: >> On Sat, 21 Jun 2008 20:54:06 -0400, the renowned Jim Flanagan >> <jflan@tampaREMOVEbay.rr.com> wrote: >> >>> Hi - >>> I'm attempting to debug a problem with an existing embedded controller >>> board. The board uses a MC68020 and uses either 1 or 2 banks of 30pin >>> simm memory. I think this is a 199? design. The board supports either >>> 1M or 4M memory. The SIMM memory is configured to be accessed as a >>> 16bit wide data bus. The 1M memory works OK, but there are read/write >>> errors when using the 4M memory. I'm confident the 4M memory that I >>> bought is compatible, as I've studied the datasheets for both 1 and 4M >>> and their topologies and access speeds are the same. No parity is used >>> in this design. Refresh (<15uSec CBR time) and access times (70nSec) >>> are the same and I've looked at the ras/cas timing and compared them >>> against the datasheet and they look like there is plenty of timing margin. >>> >>> What would you guys suggest as to how and troubleshoot this problem? >>> >>> The 4M is brand new, quality memory and the timing looks good. Where >>> would my problem possibly lie? I have not looked yet at signal >>> integrity (signal ringing, etc). I've also not looked at any potential >>> power supply problems either. I've noticed on the schematics that there >>> are no termination resistors, but I figured that this is a fairly slow >>> bus and since the 1M memory is not having any issues, that this would >>> not likely be an issue. >>> >>> Anyway, if you can offer any tips on testing the signal integrity or any >>> other ideas, it would be appreciated. >>> >>> Thanks. >>> Jim >> >> Could the refresh counter be too narrow? >> >> >> Best regards, >> Spehro Pefhany > >I'm sorry, I don't understand what you mean by 'too narrow'? According >to the 4M datasheet, using CBR should take no more than 64mSec or 15uSec >per column, assuming a square matrix (2^11). I see the refresh counter >performing a refresh cycle about every 12uSec. So, I should be OK, or am >I missing something? Thanks for the input. >Jim
Check the actual number of columns. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com