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what does "host bridge" mean?

Started by John Black August 10, 2004
I am looking into some PCI document for the development board I have, in
PCI section it mentions a lot a word, "host bridge", what exactly does
this mean? Google only gives me a bunch of products, I want to know
where I can find the terminlogy explanation.

Thanks.

I'm sure that people more experienced that I will correct me, but when I was
working with PCI, on the platform that I worked with the "host-bridge" was
an IC that served as bridge between the PowerPC data bus and the PCI data
bus.


"John Black" <black@eed.com> wrote in message
news:41191BF6.FE76CE3C@eed.com...
> I am looking into some PCI document for the development board I have, in > PCI section it mentions a lot a word, "host bridge", what exactly does > this mean? Google only gives me a bunch of products, I want to know > where I can find the terminlogy explanation. > > Thanks. >
That's the right general idea.  More commonly, the implementation only takes
up part of a chip, such as one of the support chips in an Intel architecture PC,
or it's just built into the processor, like in the more highly integrated PPC
chips.
But it is indeed a bus conversion from a processor bus to a PCI bus.  Lets a
bus-master PCI card access memory on the other side.



"&#2013266083;&#2013266082;$&#2013266085;"
<&#2013266083;&#2013266082;$&#2013266085;@phantom.com> wrote in message
news:41193317$0$22718$39cecf19@news.twtelecom.net...
> I'm sure that people more experienced that I will correct me, but when I was > working with PCI, on the platform that I worked with the "host-bridge" was > an IC that served as bridge between the PowerPC data bus and the PCI data > bus. > > > "John Black" <black@eed.com> wrote in message > news:41191BF6.FE76CE3C@eed.com... > > I am looking into some PCI document for the development board I have, in > > PCI section it mentions a lot a word, "host bridge", what exactly does > > this mean? Google only gives me a bunch of products, I want to know > > where I can find the terminlogy explanation. > > > > Thanks. > > > >
John Black <black@eed.com> wrote in message news:<41191BF6.FE76CE3C@eed.com>...
> I am looking into some PCI document for the development board I have, in > PCI section it mentions a lot a word, "host bridge", what exactly does > this mean? Google only gives me a bunch of products, I want to know > where I can find the terminlogy explanation.
The "Host Bridge" is what connects the tree of PCI busses (which are internally connected with PCI-to-PCI Bridges) to the rest of the system. Usually the processor(s) and memory are on the "other" side of the Host Bridge. On typical PC implementations, this function is embedded in the North Bridge.
David Kinsell <kinsell@poboxyz.com> wrote:
: That's the right general idea.  More commonly, the implementation only takes
: up part of a chip, such as one of the support chips in an Intel architecture PC,
: or it's just built into the processor, like in the more highly integrated PPC
chips.
: But it is indeed a bus conversion from a processor bus to a PCI bus.  Lets a
: bus-master PCI card access memory on the other side.
: 
: 
: "??$?" <??$?@phantom.com> wrote in message
news:41193317$0$22718$39cecf19@news.twtelecom.net...
:> I'm sure that people more experienced that I will correct me, but when I was
:> working with PCI, on the platform that I worked with the "host-bridge" was
:> an IC that served as bridge between the PowerPC data bus and the PCI data
:> bus.

Correct. A bridge between the sytem Local Bus and the Peripheral Component
Interconnect (PCI) bus. 

But there is more to it - there might be multiple local bus to PCI bridges
in the system. There might even be mulitple PCI buses connected either
transparent (hierarchal) or non-transparent. There might even be completely
different buses in the system, like ISA or VME. All of them require access
to the PCI bus and system memory, otherwise they wouldn't be there in the
first place. Most of them even require bus master privileges. And it is the
responsibility of the 'host bridge' to do the arbitration between the
different contenders for PCI bus time slices. Interrupt steering should
have been here too, but more often than not isn't. 


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