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Hi folks, I am a student designing an 8 bit cpu in an XCS10. I am using Visual HDL 6.7 and Xilinx ISE. Can someone tell me what is the method to link my cpu design to an internal ROM. By internal I mean a ROM made inside the Xilinx chip. I can use coregen to create the component, but will this be enough to keep Visual happy and will it be able to find the architecture when I get to ISE. and also find the coe file. Also I would like an asynchronous ROM and the coregen seems to create a sync ROM. TIA, Bill Keenan -------- This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the originator of the message. This footer also confirms that this email message has been scanned for the presence of computer viruses. Any views expressed in this message are those of the individual sender, except where the sender specifies and with authority, states them to be the views of NMIT |
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ROM Implementation
Started by ●May 20, 2002
Reply by ●May 21, 20022002-05-21
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Hi Bill. You can either instantiate the ROMs in your block diagrams or you could write synthesiable, also known as inferred ROM. If you are using the Xilinx XST tool for synthesis the manual will tell you how. If you were using Mentor Graphics tool, HDL Designer, I could be more helpful but I don't have details on Visual HDL. Sorry. Xilinx block RAMs are used to emulate ROM's in Xilinx virtex type parts. They only support synchronous behaviour. If you want asynchronous behaviour you will have to use the distributed RAM, pre load the values, and tie the write line high or low as appropriate. This will work well if your ROM is not too big. You will also need to create the address decoding. Again our synthesis tool would do this for you. I am not sure about XST in this case. I didn't see anything in the manual about it. Hope that helps a bit. Cheers. Robert Jeffery FAE Mentor Graphics (UK) -----Original Message----- From: Bill Keenan [mailto:] Sent: Monday, May 20, 2002 11:27 PM To: Subject: [fpga-cpu] ROM Implementation Hi folks, I am a student designing an 8 bit cpu in an XCS10. I am using Visual HDL 6.7 and Xilinx ISE. Can someone tell me what is the method to link my cpu design to an internal ROM. By internal I mean a ROM made inside the Xilinx chip. I can use coregen to create the component, but will this be enough to keep Visual happy and will it be able to find the architecture when I get to ISE. and also find the coe file. Also I would like an asynchronous ROM and the coregen seems to create a sync ROM. TIA, Bill Keenan ---- ---- This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the originator of the message. This footer also confirms that this email message has been scanned for the presence of computer viruses. Any views expressed in this message are those of the individual sender, except where the sender specifies and with authority, states them to be the views of NMIT To post a message, send it to: To unsubscribe, send a blank message to: ">http://docs.yahoo.com/info/terms/ |
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Reply by ●May 21, 20022002-05-21
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It's much the same in Visual. Once you generate your CoreGen part, there should be a .vho file which has an entity declaration. Create a VHDL entity with the data from the .vho file. (You're probably best off creating a custom symbol for it as well.) Leave the architecture empty, although it may behoove you to name the architecture something such as COREGEN. When you're ready to simulate, you'd export from VisualHDL and replace Visual's configuration statement for your ROM with the provided configuration in the .VHO file. I haven't don't a synthesys with the coregen files (that was someone else on the team), but I gather you'd take the .xco file and use that instead of your .vhd file. * I don't work for Summit, but I do use the tools. This should not be considered an attack or an endorsement of those tools. I'm not sure why if you're making a processor you'd want an asynch ROM. For the most part asynch parts are devices you have to work around as opposed to fitting easily into your design. Since you have the option of making the design fully synchronous, your best bet from a design standpoint is to be fully synchronous. Any time you deal with an asynch design you have to do at least 3x the work in terms of timing analysis, plus, you'll have more trouble writing the constraints to do your synthesys/PAR. I don't see any benefits whatsoever to an async ROM in a uP device. Keith > You can either instantiate the ROMs in your block diagrams or you could > write synthesiable, also known as inferred ROM. If you are using the Xilinx > XST tool for synthesis the manual will tell you how. If you were using > Mentor Graphics tool, HDL Designer, I could be more helpful but I don't have > details on Visual HDL. Sorry. > > Xilinx block RAMs are used to emulate ROM's in Xilinx virtex type parts. > They only support synchronous behaviour. If you want asynchronous behaviour > you will have to use the distributed RAM, pre load the values, and tie the > write line high or low as appropriate. This will work well if your ROM is > not too big. You will also need to create the address decoding. Again our > synthesis tool would do this for you. I am not sure about XST in this case. > I didn't see anything in the manual about it. > > Hope that helps a bit. > > Cheers. > > Robert Jeffery > FAE Mentor Graphics (UK) > > -----Original Message----- > From: Bill Keenan [mailto:] > Sent: Monday, May 20, 2002 11:27 PM > To: > Subject: [fpga-cpu] ROM Implementation > Hi folks, > I am a student designing an 8 bit cpu in an XCS10. I am using Visual HDL 6.7 > and > Xilinx ISE. > Can someone tell me what is the method to link my cpu design to an internal > ROM. > By internal I mean a ROM made inside the Xilinx chip. I can use coregen to > create > the component, but will this be enough to keep Visual happy and will it be > able > to find the architecture when I get to ISE. and also find the coe file. Also > I > would like an asynchronous ROM and the coregen seems to create a sync ROM. > TIA, > Bill Keenan > > ---- > ---- > This email and any files transmitted with it are confidential and > intended solely for the use of the individual or entity to whom > they are addressed. > If you have received this email in error please notify the > originator of the message. This footer also confirms that this > email message has been scanned for the presence of computer viruses. > > Any views expressed in this message are those of the individual > sender, except where the sender specifies and with authority, > states them to be the views of NMIT > > To post a message, send it to: > To unsubscribe, send a blank message to: > ">http://docs.yahoo.com/info/terms/ > To post a message, send it to: > To unsubscribe, send a blank message to: > > ">http://docs.yahoo.com/info/terms/ -- Keith D. Shapiro http://www.torilive.org/ |
