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Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the clock cycles of a specific C program). Those who also do the similiar work of multi-cpu (XR-16) design: please give me your kind advice and share some useful experience. I thought I need a bus arbitrator Verilog HDL program for my design. Thank you in anticipation. Contact me: --------------------------------- |
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Please help me with the XR-16 design work
Started by ●October 15, 2002
Reply by ●October 19, 20022002-10-19
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> From: Yi Zhang [mailto:] > Hi, friends, I am doing a design work of assigning as many > XR-16 CPUs on a Altera development board to see the > performance (the clock cycles of a specific C program). I can't offer any specific help. However, note that xr16 (www.fpgacpu.org/xsoc/xr16.html) is optimized for Xilinx XC4000E and derivatives. In particular, it uses distributed select RAM a.k.a. LUT RAM for its 2r1w register file. Without some rework, I don't think xr16 is a great fit for Altera FPGAs. If you are targeting Altera, consider Nios (http://www.altera.com/products/devices/nios/nio-index.html) and the Nios Dev Kit. I believe it should be possible (and perhaps even easy) to configure a multiprocessor system using SOPC Builder. Jan Gray, Gray Research LLC |
