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Hi, I am working on the spartanIIe FPGA and making use of the microblaze processor(EDK tool). My doubt is a very general one. basically the microblaze document says that cache in microblaze is implemented using Block RAM and on the other hand he also says that Block RAM can be made use of as a local on chip memory. If that is the case then my doubt is...- How can BRAM be used as a cache as well as an onchip memory? I ask this because, while making a design using 'Base System Builder' in EDK Tool, I came across two fields, one was to enable cache & another to have local data & instruction memory(which obviously refers to BRAM). But while indicating the size of cache it says that BRAM resources of FPGA will be used for cache. Now, is it possible to have part of BRAM act as cache & the other part as local memory?? I even tried exhausting the local memory size by making it 8KB(this is the total capacity of BRAM in spartanIIe) and enabled cache as well, but surprisingly i could generate the bitstream without encountering any errors. I got one warning though i.e. "WARNING:Data2MEM:47 - Not all BitLanes in ADDRESS_BLOCK 'bram_block_0' have BMM location constraints. Some data for this ADDRESS_BLOCK may have been lost during BIT file replacement." What does this warning mean? Could someone please explain how cache is implmented if not for BRAM?? Waiting for your kind response, thanks, ponnmozhi. |
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doubt in configuration of cache in fpga
Started by ●February 4, 2004
Reply by ●February 6, 20042004-02-06
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I guess there are some hidden BRAMs in the chip that can be used by processor core only. The 8KB which you exhausted, must be the total BRAM size AVAILABLE to USER( i.e user can instantiate BRAM component in his HDL design or write HDL code to infer BRAM). Thanks, Bharath -------------------------- Disclaimer: the opinions expressed here are purely Personal -------------------------- -----Original Message----- From: ponnmozhi [mailto:] Sent: Wednesday, February 04, 2004 10:44 AM To: Subject: [fpga-cpu] doubt in configuration of cache in fpga Hi, I am working on the spartanIIe FPGA and making use of the microblaze processor(EDK tool). My doubt is a very general one. basically the microblaze document says that cache in microblaze is implemented using Block RAM and on the other hand he also says that Block RAM can be made use of as a local on chip memory. If that is the case then my doubt is...- How can BRAM be used as a cache as well as an onchip memory? I ask this because, while making a design using 'Base System Builder' in EDK Tool, I came across two fields, one was to enable cache & another to have local data & instruction memory(which obviously refers to BRAM). But while indicating the size of cache it says that BRAM resources of FPGA will be used for cache. Now, is it possible to have part of BRAM act as cache & the other part as local memory?? I even tried exhausting the local memory size by making it 8KB(this is the total capacity of BRAM in spartanIIe) and enabled cache as well, but surprisingly i could generate the bitstream without encountering any errors. I got one warning though i.e. "WARNING:Data2MEM:47 - Not all BitLanes in ADDRESS_BLOCK 'bram_block_0' have BMM location constraints. Some data for this ADDRESS_BLOCK may have been lost during BIT file replacement." What does this warning mean? Could someone please explain how cache is implmented if not for BRAM?? Waiting for your kind response, thanks, ponnmozhi. To post a message, send it to: To unsubscribe, send a blank message to: Yahoo! Groups Links |
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Reply by ●February 6, 20042004-02-06
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ponnmozhi:
I think there are 14 x 512byte BRAMS in the 200K Gate Spartan2 probably more in the 300K gate Spartan 2e. I'm not familiar with the Microblaze, but I am assuming the BRAMS are used as microcode storage. BRAMS can be initiazed as ROM. The BRAMS can be configured as 4 bits, 8 bits or 16 bits wide in the Web Pack ISE libraries. You can also use them as Dual port RAMs. I would not imagine you would have more than 256 states in the MicroBlaze microcode, so its just a matter of how many bits wide the microcode ROM needs to be. You should have plenty of BRAMS spare for use as cache as 14 x 16bits = more bits than you are likely to need for microcode. J. ponnmozhi wrote: >Hi, >I am working on the spartanIIe FPGA and making use of the microblaze >processor(EDK tool). My doubt is a very general one. basically the >microblaze document says that cache in microblaze is implemented >using Block RAM and on the other hand he also says that Block RAM can >be made use of as a local on chip memory. >If that is the case then my doubt is...- >How can BRAM be used as a cache as well as an onchip memory? > >I ask this because, while making a design using 'Base System Builder' >in EDK Tool, I came across two fields, one was to enable cache & >another to have local data & instruction memory(which obviously >refers to BRAM). But while indicating the size of cache it says that >BRAM resources of FPGA will be used for cache. Now, is it possible to >have part of BRAM act as cache & the other part as local memory?? >I even tried exhausting the local memory size by making it 8KB(this >is the total capacity of BRAM in spartanIIe) and enabled cache as >well, but surprisingly i could generate the bitstream without >encountering any errors. I got one warning though i.e. > >"WARNING:Data2MEM:47 - Not all BitLanes in >ADDRESS_BLOCK 'bram_block_0' have BMM location constraints. >Some data for this ADDRESS_BLOCK may have been lost during BIT file >replacement." > >What does this warning mean? > >Could someone please explain how cache is implmented if not for BRAM?? > >Waiting for your kind response, > >thanks, >ponnmozhi. > |
Reply by ●February 6, 20042004-02-06
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Hi Ponnmozhi, The BRAM in the FPGA is as standard SRAM. SRAM can be used for storing instruction and data but also used for creating caches. The same BRAM can't be used for both cache and standard memory at the same time. They are seperate BRAMs. ex. Creating a 8kb of LMB memory requires 4 BRAM (VII,VIIPro,S3) or 16 BRAM (V,VE,S2,S2E). To create a 8kb of instruction caches requires 5 BRAM (VII,VIIPro,S3) or 18 BRAM (V,VE,S2,S2E). I think that you can ignore the warnig fro Data2MEM. I will check with the hotline guys. Gan ponnmozhi wrote: >Hi, >I am working on the spartanIIe FPGA and making use of the microblaze >processor(EDK tool). My doubt is a very general one. basically the >microblaze document says that cache in microblaze is implemented >using Block RAM and on the other hand he also says that Block RAM can >be made use of as a local on chip memory. >If that is the case then my doubt is...- >How can BRAM be used as a cache as well as an onchip memory? > >I ask this because, while making a design using 'Base System Builder' >in EDK Tool, I came across two fields, one was to enable cache & >another to have local data & instruction memory(which obviously >refers to BRAM). But while indicating the size of cache it says that >BRAM resources of FPGA will be used for cache. Now, is it possible to >have part of BRAM act as cache & the other part as local memory?? >I even tried exhausting the local memory size by making it 8KB(this >is the total capacity of BRAM in spartanIIe) and enabled cache as >well, but surprisingly i could generate the bitstream without >encountering any errors. I got one warning though i.e. > >"WARNING:Data2MEM:47 - Not all BitLanes in >ADDRESS_BLOCK 'bram_block_0' have BMM location constraints. >Some data for this ADDRESS_BLOCK may have been lost during BIT file >replacement." > >What does this warning mean? > >Could someone please explain how cache is implmented if not for BRAM?? > >Waiting for your kind response, > >thanks, >ponnmozhi. > > >To post a message, send it to: >To unsubscribe, send a blank message to: >Yahoo! Groups Links > > |
Reply by ●February 6, 20042004-02-06
