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hi, I am back with my cache problem. [this is implementing a design using the microblaze using EDK tool (xilinx Platform Studio]. Since there are fixed possible sizes of BRAM which can be assigned,like for spartanIIe 2,4,8 KB First I tried executing with cache disabled- 1. For ilmb & idlmb I assigned address 0x00000000 to 0x000007FF (for BRAM size of 2KB) I could generate the bitstream without error. The following data was displayed:- Device utilization summary: Number of External GCLKIOBs 1 out of 4 - 25% Number of External IOBs 3 out of 325 - 1% Number of LOCed External IOBs 3 out of 3 - 100% **NUMBER of BLOCKRAMs 4 out of 16 - 25% Number of SLICEs 744 out of 3072 - 24% Number of GCLKs 1 out of 4 - 25% All the above data are as expected, as can be seen, BRAMs used are 4 i.e (4*4Kb)/8= 2KB,which is what we had intended to use. 2. Next I did with ilmb & dlmb address of 0x00000000 to 0x00000FFF( for BRAM size of 4KB) Here again I got similar results without any error Device utilization summary: [... Number of BLOCKRAMs 8 out of 16 - 50% ..] The size of BRAM used is again fine i.e (8*4Kb)/8= 4KB. 3. Next with ilmb & dlmb addr of 0x00000000 to 0x00001FFF ( for BRAM size of 8KB) Device utilization summary: [.. Number of BLOCKRAMs 16 out of 16 - 100% ..] The size of BRAM is (16*4Kb)/8=8KB. 4. Since there was a choice of using 16KB I tried with ilmb & dlmb addr of 0x00000000 to 0x00003FFF for a BRAM size of 16KB. But I got an ERROR at bitgeneration with the following data: [.. Number of Block RAMs: 32 out of 16 - 200% (OVERMAPPED) ..] next I tried with cache enabled & I got the following results. 5. For ilmb & dlmb address range 0x00000000 to 0x000007FF & with ICACHE & DCACHE byte size of 2048. I could generate the bitfile with 8 warning of the following nature:- WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp microblaze_0/microblaze_0/ICache_I1/Mram_Tag_Memory_inst_ramb_5 is not connected. 6. Addrress range of ilmb & dlmb 0x00000000 to 0x000007FF with ICACHE & DCACHE byte size of 4096 I could generate the bitfile with 3 warnings of same nautre as given above. [.. Number of Block RAMs: 15 out of 16 ..] But I dont understand this, why are the number of BRAMs so asymmetrically utilised for cache? I mean for a size of 4KB, it should have used 8 BRAMs as seen in case no.2 i.e locAL bram SIZE IS 2KB & cache of 4KB so totally for 6KB of memory,12 BRAMs are needed but it is indicated as 15 BRAMs?? 7. Address of ilmb & dlmb 0x00000000 to 000007FF with ICACHE & DCACHE byte size of 8192 This gave error saying that the design is too large.& there was no bit generation [.. Number of Block RAMs: 25 out of 16 - 156% (OVERMAPPED) ..] 8. address of ilmb & dlmb 0x00000000 to 0x00000FFF & ICACHE & DCACHE byte size of 2048 I could generate the bitstream with few warnings as in case 5. WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp microblaze_0/microblaze_0/ICache_I1/Mram_Tag_Memory_inst_ramb_5 is not connected. Device utilization summary: [.. Number of BLOCKRAMs 14 out of 16 - 87% ..] here again shouldnt the number of BRAMs used be 12??? 9. address of ilmb & dlmb 0x00000000 to 0x00000FFF with ICACHE & DCACHE byte size of 4096. This gave error: ERROR:Pack:18 - The design is too large for the given device and package. [.. Number of Block RAMs: 19 out of 16 - 118% (OVERMAPPED) ..] 10. address ilmb & dlmb of 0x00000000 to 0x00001FFF with ICACHE & DCACHE byte size of 2048. this too gave an error :ERROR:Pack:18 - The design is too large for the given device and package. [.. Number of Block RAMs: 22 out of 16 - 137% (OVERMAPPED) ..] There is one thing I could make out from this,i.e, once the bram is exhausted, cache cannot be used, which is what is expected. i.e only a total of around 8KB(for spartanIIe) is allowed for either BRAM or cache or both together. but I dont understand the number of BRAMs used when cache is enabled??? Also , the warning which i spoke about in my previous mail i.e " WARNING:Data2MEM:47 - Not all BitLanes in ADDRESS_BLOCK 'bram_block_0' have BMM location constraints.Some data for this ADDRESS_BLOCK may have been lost during BIT file replacement." This has been corrected in the new service pack of edk6.1i. But above all the number OF brams used with cache enabled is very puzzling??? waiting for ur response, thanks, ponnmozhi. |
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BRAM utilisation for CACHE.
Started by ●February 11, 2004
Reply by ●February 11, 20042004-02-11
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Hi, When implementing an instruction cache, MicroBlaze will need BRAM for storing the cached instruction but also BRAM for maintaining the tag information. The number of BRAM needed for the tag is dependent on the cache size and the address range that the cache is covering. Each BRAM in S2E is 4kbit or rather 0.5 KByte. A 4 KByte cache needs 8 BRAM for storing the instructions. Since each instruction is 4 bytes and there is a tag for each instruction, there is 1024 tags in the cache. In the tag BRAM, the valid and the lock bit is also stored. So the number of BRAMs needed for the tag is (2 + tag address). If you want the caches to cover 1MByte of address range, the tag address has to be (1MByte/4Kbyte) = 256 => 8 bits 8 bits + 2 for the valid and lock bits requires 10 bits, this will require 3 BRAMs for the tag memory. This is the same for the data caches. But the minimum data cache for S2E is 2kbyte since the cache needs to support byte writes. This requires that the number of BRAM can be less than 4 since the BRAM doesn't support byte enables. Gan ponnmozhi wrote: >hi, >I am back with my cache problem. >[this is implementing a design using the microblaze using EDK tool >(xilinx Platform Studio]. >Since there are fixed possible sizes of BRAM which can be >assigned,like for spartanIIe 2,4,8 KB >First I tried executing with cache disabled- > >1. For ilmb & idlmb I assigned address >0x00000000 to 0x000007FF (for BRAM size of 2KB) > >I could generate the bitstream without error. The following data was >displayed:- > >Device utilization summary: > >Number of External GCLKIOBs 1 out of 4 - 25% >Number of External IOBs 3 out of 325 - 1% >Number of LOCed External IOBs 3 out of 3 - 100% >**NUMBER of BLOCKRAMs 4 out of 16 - 25% >Number of SLICEs 744 out of 3072 - 24% >Number of GCLKs 1 out of 4 - 25% > >All the above data are as expected, as can be seen, BRAMs used are 4 >i.e (4*4Kb)/8= 2KB,which is what we had intended to use. > >2. Next I did with ilmb & dlmb address of >0x00000000 to 0x00000FFF( for BRAM size of 4KB) > >Here again I got similar results without any error >Device utilization summary: > >[... >Number of BLOCKRAMs 8 out of 16 - 50% >..] > >The size of BRAM used is again fine i.e (8*4Kb)/8= 4KB. > >3. Next with ilmb & dlmb addr of >0x00000000 to 0x00001FFF ( for BRAM size of 8KB) > >Device utilization summary: > >[.. >Number of BLOCKRAMs 16 out of 16 - 100% >..] > >The size of BRAM is (16*4Kb)/8=8KB. > >4. Since there was a choice of using 16KB I tried with ilmb & dlmb >addr of 0x00000000 to 0x00003FFF for a BRAM size of 16KB. > >But I got an ERROR at bitgeneration with the following data: >[.. >Number of Block RAMs: 32 out of 16 - 200% (OVERMAPPED) >..] >next I tried with cache enabled & I got the following results. > >5. For ilmb & dlmb address range >0x00000000 to 0x000007FF & with >ICACHE & DCACHE byte size of 2048. > >I could generate the bitfile with 8 warning of the following nature:- > >WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin >DOB1 of comp >microblaze_0/microblaze_0/ICache_I1/Mram_Tag_Memory_inst_ramb_5 is >not connected. >6. Addrress range of ilmb & dlmb >0x00000000 to 0x000007FF with >ICACHE & DCACHE byte size of 4096 > >I could generate the bitfile with 3 warnings of same nautre as given >above. > >[.. >Number of Block RAMs: 15 out of 16 >..] > >But I dont understand this, why are the number of BRAMs so >asymmetrically utilised for cache? I mean for a size of 4KB, it >should have used 8 BRAMs as seen in case no.2 >i.e >locAL bram SIZE IS 2KB & cache of 4KB so totally for 6KB of memory,12 >BRAMs are needed but it is indicated as 15 BRAMs?? > >7. Address of ilmb & dlmb >0x00000000 to 000007FF with >ICACHE & DCACHE byte size of 8192 > >This gave error saying that the design is too large.& there was no >bit generation > >[.. >Number of Block RAMs: 25 out of 16 - 156% (OVERMAPPED) >..] >8. address of ilmb & dlmb >0x00000000 to 0x00000FFF & >ICACHE & DCACHE byte size of 2048 > >I could generate the bitstream with few warnings as in case 5. > >WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin >DOB1 of comp >microblaze_0/microblaze_0/ICache_I1/Mram_Tag_Memory_inst_ramb_5 is >not connected. > >Device utilization summary: >[.. >Number of BLOCKRAMs 14 out of 16 - 87% >..] > >here again shouldnt the number of BRAMs used be 12??? >9. address of ilmb & dlmb >0x00000000 to 0x00000FFF with >ICACHE & DCACHE byte size of 4096. > >This gave error: ERROR:Pack:18 - The design is too large for the >given device and package. > >[.. >Number of Block RAMs: 19 out of 16 - 118% (OVERMAPPED) >..] >10. address ilmb & dlmb of >0x00000000 to 0x00001FFF with >ICACHE & DCACHE byte size of 2048. > >this too gave an error :ERROR:Pack:18 - The design is too large for >the given device and package. > >[.. >Number of Block RAMs: 22 out of 16 - 137% (OVERMAPPED) >..] >There is one thing I could make out from this,i.e, once the bram is >exhausted, cache cannot be used, which is what is expected. i.e only >a total of around 8KB(for spartanIIe) is allowed for either BRAM or >cache or both together. > >but I dont understand the number of BRAMs used when cache is >enabled??? > >Also , the warning which i spoke about in my previous mail i.e > >" >WARNING:Data2MEM:47 - Not all BitLanes in >ADDRESS_BLOCK 'bram_block_0' have BMM location constraints.Some data >for this ADDRESS_BLOCK may have been lost during BIT file >replacement." > >This has been corrected in the new service pack of edk6.1i. > >But above all the number OF brams used with cache enabled is very >puzzling??? > >waiting for ur response, >thanks, >ponnmozhi. > >To post a message, send it to: >To unsubscribe, send a blank message to: >Yahoo! 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