Dose Altera Nios support hardware-based multi-thread and how?

Started by qfmyue ●December 2, 2003

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, it has the sliding register file windows technology. So I think it maybe support hardware multi-thread technology,but I can't find the relatial manual or reference. Dose Altera Nios support hardware-based multi-thread and how??

Reply by Martin Schoeberl ●April 10, 20042004-04-10

> In Altera development kits ,I can't find the description about it. > The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, > it has the sliding register file windows technology. So I think it > maybe support hardware multi-thread technology,but I can't find the > relatial manual or reference. > Dose Altera Nios support hardware-based multi-thread and how?? No, there is no hardware support for multi-threading. Not more than a traditional timer interrupt. The sliding register window is used for faster function call and return. Martin ---------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/

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