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I am looking into the design of a processor to implement P4 Pascal. Since I plan to use the Spartan 3 Starter Board it appears I should probably design around the 32 bit memory system and that is more than adequate for the stack machine and integer arithmetic. Strings and sets would be variable length, multiple word variables. At some point, way down the line, I should implement floating point math. The usual suspects: add, subtract, multiply, divide, sin, cos, atn, exp and log. For a first cut, 32 bit floating point will probably be adequate although 64 bit would probably come later. Or maybe 64 bit is the only flavor. Are there any free sources around for a floating point package that could be implemented on an FPGA? I could use a co-processor chip, I suppose, but that seems to defeat the purpose of my project. I could also grab the code for some microprocessor or even the PIC but I am looking for something a little more FPGA centric. Thanks for any hints you may have! |
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Floating Point Arithmetic
Started by ●October 19, 2004
Reply by ●October 19, 20042004-10-19
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On Tue, 2004-10-19 at 11:45, rtstofer wrote: > Are there any free sources around for a floating point package that > could be implemented on an FPGA? The open-source JHDL (www.jhdl.org) system has a library which includes some floating-point cores. Carl Witty |
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Reply by ●October 19, 20042004-10-19
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--- In , Carl Witty <cwitty@n...> wrote: > On Tue, 2004-10-19 at 11:45, rtstofer wrote: > > Are there any free sources around for a floating point package that > > could be implemented on an FPGA? > > The open-source JHDL (www.jhdl.org) system has a library which includes > some floating-point cores. > > Carl Witty Thanks for the lead. It looks like BYU is doing some very interesting work in the area of application specific processors. |
Reply by ●October 19, 20042004-10-19
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> At some point, way down the line, I should implement floating point > math. The usual suspects: add, subtract, multiply, divide, sin, > Are there any free sources around for a floating point package that > could be implemented on an FPGA? I could use a co-processor chip, I There's an FPU co-processor core available on OPENCORES! 32-bit IEEE754 compatible. Alas, if only the free Xilinx Webpack supported an FPGA with an embedded PowerPC core. |
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Reply by ●October 20, 20042004-10-20
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I'm going to take a look at Opencores. Floating point is an afterthought. It won't be necessary for a couple of years, if then. There is a lot of work to do to get the processor running and application code written for the operating system. --- In , "Rob Finch" <robfinch@s...> wrote: > > > At some point, way down the line, I should implement floating point > > math. The usual suspects: add, subtract, multiply, divide, sin, > > > Are there any free sources around for a floating point package that > > could be implemented on an FPGA? I could use a co-processor chip, I > > There's an FPU co-processor core available on OPENCORES! > 32-bit IEEE754 compatible. > > Alas, if only the free Xilinx Webpack supported an FPGA with an > embedded PowerPC core. |
Reply by ●October 20, 20042004-10-20
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At 02:45 PM 10/19/2004, you wrote:
>I am looking into the design of a processor to
implement P4 Pascal. >Since I plan to use the Spartan 3 Starter Board it appears I should >probably design around the 32 bit memory system and that is more than >adequate for the stack machine and integer arithmetic. Strings and >sets would be variable length, multiple word variables. I am curious, why would you want to design your own CPU when there are so many available? Wouldn't it work well to "interpret" the Pascal or compile to native code? The microBlaze or NIOS-II are very optimized for FPGAs and will likely do a better job than your own. What special features would you be using that these don't have? BTW, you can add your own special instructions to both of these processors, IIRC. Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX |
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Reply by ●October 20, 20042004-10-20
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The really short answer: I just want to design a retro machine, like the CP/M project I just finished that uses the T80 core, but in this case everything is from scratch: compiler, loader, OS, everything. All written in Pascal because the underlying instruction set is a P machine. Actually, the compiler will start out from the original P4 implementation kit - I am certainly not going to reinvent that part. It will look and feel a lot like the UCSD Pascal system circa 1980 - brings back memories of younger days. Just for fun, I guess. Because there is no way an FPGA, even structured to optimize the stack machine, can keep up with a 3.6 GHz Pentium even with a sub-optimal interpreter written in C. As I see it, the entire machine will run on the Spartan 3 Starter Board, probably use the graphics component that comes with the board and the 256K of 32bit RAM will be more than adequate. Hang a CF on one of the ports and the machine is ready to go. Worst case it should be an order of magnitude faster than the system as originally implemented on the CDC 6600 with the exception of floating point arithmetic. Yes, microBlaze or XSOC would be good platforms but they wouldn't be my design and I am not sure which would take longer: understanding these full featured, no holds barred designs or creating a very simple machine from scratch. Oh, and I would have to buy microBlaze and it costs far more than I want to spend. And I wouldn't even get the source! Being retired, I have a lot of time to work on these things. No hurry, no schedule, no boss. > I am curious, why would you want to design your own CPU when there are so > many available? Wouldn't it work well to "interpret" the Pascal or compile > to native code? The microBlaze or NIOS-II are very optimized for FPGAs and > will likely do a better job than your own. > > What special features would you be using that these don't have? BTW, you > can add your own special instructions to both of these processors, IIRC. > > Rick Collins > > rick.collins@a... > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX |
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Reply by ●October 20, 20042004-10-20
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rtstofer wrote: > > The really short answer: I just want to design a retro machine, like > the CP/M project I just finished that uses the T80 core, but in this > case everything is from scratch: compiler, loader, OS, everything. > All written in Pascal because the underlying instruction set is a P > machine. Actually, the compiler will start out from the original P4 > implementation kit - I am certainly not going to reinvent that part. > It will look and feel a lot like the UCSD Pascal system circa 1980 - > brings back memories of younger days. > > Just for fun, I guess. Because there is no way an FPGA, even > structured to optimize the stack machine, can keep up with a 3.6 GHz > Pentium even with a sub-optimal interpreter written in C. Yes but how fast is a 3.6 GHZ machine for real when you find out how slow real memory acesss is. FPGA's are about 1/10 that speed for gate level logic. A 100 ns ( 10 Mhz clock) sounds like realistic goal for this, and a realistic computing goal. That is a realistic goal since P-machines are rare. |
Reply by ●October 21, 20042004-10-21
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At 09:45 PM 10/20/2004, you wrote:
>The really short answer: I just want to design a
retro machine, like >the CP/M project I just finished that uses the T80 core, but in this >case everything is from scratch: compiler, loader, OS, everything. >All written in Pascal because the underlying instruction set is a P >machine. Actually, the compiler will start out from the original P4 >implementation kit - I am certainly not going to reinvent that part. >It will look and feel a lot like the UCSD Pascal system circa 1980 - >brings back memories of younger days. "Just for the fun of it" is a perfectly good reason. :) >Just for fun, I guess. Because there is no way an FPGA, even >structured to optimize the stack machine, can keep up with a 3.6 GHz >Pentium even with a sub-optimal interpreter written in C. Oh, I think it is the other way around. A 3.6 GHz Pentium will have a hard time fitting into the same footprint as an FPGA and a single Flash ROM with a linear regulator. I expect an FPGA CPU board can be smaller than the heat sink on the Pentium and likely use less power than the fan! >As I see it, the entire machine will run on the Spartan 3 Starter >Board, probably use the graphics component that comes with the board >and the 256K of 32bit RAM will be more than adequate. Hang a CF on >one of the ports and the machine is ready to go. Worst case it should >be an order of magnitude faster than the system as originally >implemented on the CDC 6600 with the exception of floating point >arithmetic. > >Yes, microBlaze or XSOC would be good platforms but they wouldn't be >my design and I am not sure which would take longer: understanding >these full featured, no holds barred designs or creating a very simple >machine from scratch. Oh, and I would have to buy microBlaze and it >costs far more than I want to spend. And I wouldn't even get the source! Sounds like you are not really interested, but there are open source versions of both NIOS and mblaze out there. Check in comp.arch.fpga if you want to learn more about them. >Being retired, I have a lot of time to work on these things. No >hurry, no schedule, no boss. Yes, that part sounds nice. I am working on a not so retro CPU, a stack processor that is intended to run Forth. It is very minimal and my goal is to get the speed up to higher than 60 MHz. All memory is internal to the FPGA and it is targeted to both the Altera ACEX and the Spartan 3. Looks like I will be buying a version of MPE forth to port to this processor. Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX |
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Reply by ●October 21, 20042004-10-21
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For the fun of it... I started wire-wrapping RTL back in the late '60s and I couldn't even imagine what it would take to build a real computer. I remember some of the early minicomputers that used several boards full of TTL and magnetic memory. I had a LOT of experience with the IBM 1130 and a ton of documentation. So, I took some 74xxx, some fusible proms and built an emulation. Memory, like the 2102, wasn't available in my price range for several more years and by that time the Altair 8800 was available si I gave up on the 1130. Today, a single chip can have an 1130 and a Z80 in the same package - absolutely amazing. I plan to get back to that 1130 and have starting accumulating the documentation. Right after the P machine. I was sort of planning on a lot more speed than 10 MHz. Heck, the T80 core runs reliably at 14 MHz and could probably do more if I used the high slew rate on the external RAM. I was thinking about at least 20 MHz for the stack machine. The SRAM on the board is rated at 10 nS and the Xtal is 50 MHz. I will look at the other processors. True, I want to roll my own but there are too many good ideas out there to just ignore them. --- In , Arius - Rick Collins <dsprelated@a...> wrote: > At 09:45 PM 10/20/2004, you wrote: > >The really short answer: I just want to design a retro machine, like > >the CP/M project I just finished that uses the T80 core, but in this > >case everything is from scratch: compiler, loader, OS, everything. > >All written in Pascal because the underlying instruction set is a P > >machine. Actually, the compiler will start out from the original P4 > >implementation kit - I am certainly not going to reinvent that part. > >It will look and feel a lot like the UCSD Pascal system circa 1980 - > >brings back memories of younger days. > > "Just for the fun of it" is a perfectly good reason. :) > >Just for fun, I guess. Because there is no way an FPGA, even > >structured to optimize the stack machine, can keep up with a 3.6 GHz > >Pentium even with a sub-optimal interpreter written in C. > > Oh, I think it is the other way around. A 3.6 GHz Pentium will have a hard > time fitting into the same footprint as an FPGA and a single Flash ROM with > a linear regulator. I expect an FPGA CPU board can be smaller than the > heat sink on the Pentium and likely use less power than the fan! > >As I see it, the entire machine will run on the Spartan 3 Starter > >Board, probably use the graphics component that comes with the board > >and the 256K of 32bit RAM will be more than adequate. Hang a CF on > >one of the ports and the machine is ready to go. Worst case it should > >be an order of magnitude faster than the system as originally > >implemented on the CDC 6600 with the exception of floating point > >arithmetic. > > > >Yes, microBlaze or XSOC would be good platforms but they wouldn't be > >my design and I am not sure which would take longer: understanding > >these full featured, no holds barred designs or creating a very simple > >machine from scratch. Oh, and I would have to buy microBlaze and it > >costs far more than I want to spend. And I wouldn't even get the source! > > Sounds like you are not really interested, but there are open source > versions of both NIOS and mblaze out there. Check in comp.arch.fpga if you > want to learn more about them. > >Being retired, I have a lot of time to work on these things. No > >hurry, no schedule, no boss. > > Yes, that part sounds nice. I am working on a not so retro CPU, a stack > processor that is intended to run Forth. It is very minimal and my goal is > to get the speed up to higher than 60 MHz. All memory is internal to the > FPGA and it is targeted to both the Altera ACEX and the Spartan 3. Looks > like I will be buying a version of MPE forth to port to this processor. > Rick Collins > > rick.collins@a... > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX |
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