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http://www.niktech.com Hardware Features Data Path Width 32 bits Most instructions are 16 bit. PC Relative jump instructions are 32 bit. Four stage pipeline. Von Neumann Architecture (Data and Instruction in the same address space). Sixteen, 32 bit General Purpose Registers. Four USER defined instructions (with Register File Write back capability). Parallel execution of independent Load/Store, Multiply/Shift , User Defined Instructions and ALU instructions (In order issue; Out of order completion) Some Conditional Instructions (Reduces branches & increases code density). Built in 32 bit Timer. Power Down Mode. 32x32 Multiplier (Multi cycle execution). Software Development Tools GNU Assembler, Linker (binutils) GCC (C Compiler) GDB (Debugger) and Instruction Set Simulator Standalone C-Library (RedHat newlib) Modified version of DietLibc Size and Performance. Netlists for the current implementation is available for XILINX Virtex,Spartan-II and Spartan-IIE; it utilizes 1375 LUTs (809 slices); the size includes a 32 bit timer and a 32x32 bit LUT based multiplier. The design has been tested to operate at 60MHZ on a Spartan-II (speed grade -6). Netlists, Documentation and Development tools can be downloaded from http://www.niktech.com. |
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ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
Started by ●October 15, 2004
Reply by ●December 17, 20042004-12-17
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I've take a look to your web but I can't find any information about
licensing. What kind of license do you have? Is it a free processor? Best regards, Javier Basilio Pez Ramas > -----Mensaje original----- > De: sandeep94404 [mailto:] > Enviado el: viernes, 15 de octubre de 2004 19:14 > Para: > Asunto: [fpga-cpu] ANN: Introducing MANIK - a 32 bit Soft-Core RISC > Processor > http://www.niktech.com > > Hardware Features > > Data Path Width 32 bits > Most instructions are 16 bit. PC Relative jump instructions > are 32 bit. > Four stage pipeline. > Von Neumann Architecture (Data and Instruction in the same > address space). > Sixteen, 32 bit General Purpose Registers. > Four USER defined instructions (with Register File Write > back capability). > Parallel execution of independent Load/Store, Multiply/Shift , > User Defined Instructions and ALU instructions > (In order issue; Out of order completion) > Some Conditional Instructions (Reduces branches & increases > code density). > Built in 32 bit Timer. > Power Down Mode. > 32x32 Multiplier (Multi cycle execution). > > Software Development Tools > GNU Assembler, Linker (binutils) > GCC (C Compiler) > GDB (Debugger) and Instruction Set Simulator > Standalone C-Library (RedHat newlib) > Modified version of DietLibc > > Size and Performance. > > Netlists for the current implementation is available for XILINX > Virtex,Spartan-II and Spartan-IIE; it utilizes 1375 LUTs (809 > slices); the size includes a 32 bit timer and a 32x32 bit LUT > based multiplier. > > The design has been tested to operate at 60MHZ on a Spartan-II > (speed grade -6). > > Netlists, Documentation and Development tools can be downloaded > from http://www.niktech.com. > > > To post a message, send it to: > To unsubscribe, send a blank message to: > > Yahoo! Groups Links |
