Hi all!
I want to know the most optimal way to implement FIFO/LRU/Random in
hardware. I am designing a cache and i need to implement these as
replacement algorithms. I guess this makes clear why i want a fast
hardware solution for implementing these.
regards,
mnsharif
Optimal Hardware Implementation FIFO/LRU/Random Algos
Started by ●June 2, 2005
Reply by ●June 3, 20052005-06-03
invincible1138 wrote:
>Hi all!
>
>I want to know the most optimal way to implement FIFO/LRU/Random in
>hardware. I am designing a cache and i need to implement these as
>replacement algorithms. I guess this makes clear why i want a fast
>hardware solution for implementing these.
>
>regards,
>mnsharif
>
What type of fifo , which LRU , which random in what hardware ?
For what purpose ?
For what parameter ? speed , gate count , area , reliabilty , error
checking ?
Makes what clear ?
Your post makes nothing clear
Alex
>Hi all!
>
>I want to know the most optimal way to implement FIFO/LRU/Random in
>hardware. I am designing a cache and i need to implement these as
>replacement algorithms. I guess this makes clear why i want a fast
>hardware solution for implementing these.
>
>regards,
>mnsharif
>
What type of fifo , which LRU , which random in what hardware ?
For what purpose ?
For what parameter ? speed , gate count , area , reliabilty , error
checking ?
Makes what clear ?
Your post makes nothing clear
Alex
Reply by ●June 3, 20052005-06-03
> invincible1138 wrote:
>
> >Hi all!
> >
> >I want to know the most optimal way to implement
> FIFO/LRU/Random in
> >hardware. I am designing a cache and i need to implement
> these as
(...)
FIFO - implement as a ring register, exactly as you do in
software. You can use built-in memory blocks then. Will be
in theory slower than chained D flip-flop blocks, but I
suspect this won't show in FPGA;
LRU - what is this?
Random - do it with Linear Shift Register;
___________________________________________________________
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>
> >Hi all!
> >
> >I want to know the most optimal way to implement
> FIFO/LRU/Random in
> >hardware. I am designing a cache and i need to implement
> these as
(...)
FIFO - implement as a ring register, exactly as you do in
software. You can use built-in memory blocks then. Will be
in theory slower than chained D flip-flop blocks, but I
suspect this won't show in FPGA;
LRU - what is this?
Random - do it with Linear Shift Register;
___________________________________________________________
Yahoo! Messenger - NEW crystal clear PC to PC calling worldwide with voicemail http://uk.messenger.yahoo.com
Reply by ●June 3, 20052005-06-03
--- In fpga-cpu@fpga..., Tomasz Sztejka <sztejkat@y...> wrote:
> > invincible1138 wrote:
> >
> > >Hi all!
> > >
> > >I want to know the most optimal way to implement
> > FIFO/LRU/Random in
> > >hardware. I am designing a cache and i need to implement
> > these as
> (...)
> FIFO - implement as a ring register, exactly as you do in
> software. You can use built-in memory blocks then. Will be
> in theory slower than chained D flip-flop blocks, but I
> suspect this won't show in FPGA;
> LRU - what is this?
> Random - do it with Linear Shift Register; >
> ___________________________________________________________
> Yahoo! Messenger - NEW crystal clear PC to PC calling worldwide
with voicemail http://uk.messenger.yahoo.com
Hey Tomasz
Yeah! Linear Shift Register for FIFO... exactly, thats what i was
looking for Random, thanx
and for FIFO, i read up a little material after posting this topic, i
realized it was really trivial to implement, almost the same as in
software.
By LRU, i mean, Least Recently Used.
regards,
mnsharif
> > invincible1138 wrote:
> >
> > >Hi all!
> > >
> > >I want to know the most optimal way to implement
> > FIFO/LRU/Random in
> > >hardware. I am designing a cache and i need to implement
> > these as
> (...)
> FIFO - implement as a ring register, exactly as you do in
> software. You can use built-in memory blocks then. Will be
> in theory slower than chained D flip-flop blocks, but I
> suspect this won't show in FPGA;
> LRU - what is this?
> Random - do it with Linear Shift Register; >
> ___________________________________________________________
> Yahoo! Messenger - NEW crystal clear PC to PC calling worldwide
with voicemail http://uk.messenger.yahoo.com
Hey Tomasz
Yeah! Linear Shift Register for FIFO... exactly, thats what i was
looking for Random, thanx
and for FIFO, i read up a little material after posting this topic, i
realized it was really trivial to implement, almost the same as in
software.
By LRU, i mean, Least Recently Used.
regards,
mnsharif
Reply by ●June 3, 20052005-06-03
--- In fpga-cpu@fpga..., Alex Gibson <yahoo@a...> wrote:
> invincible1138 wrote:
>
> >Hi all!
> >
> >I want to know the most optimal way to implement FIFO/LRU/Random
in
> >hardware. I am designing a cache and i need to implement these as
> >replacement algorithms. I guess this makes clear why i want a fast
> >hardware solution for implementing these.
> >
> >regards,
> >mnsharif
> >
> What type of fifo , which LRU , which random in what hardware ?
> For what purpose ?
>
> For what parameter ? speed , gate count , area , reliabilty ,
error
> checking ?
>
> Makes what clear ?
>
> Your post makes nothing clear
>
> Alex
Hey Alex,
By hardware i meant FPGA, offcourse i m not talking about PCB or ASIC
in fpga-cpu forum
By FIFO (first in first out), Random and LRU (least recently used) i
meant the replacemnt algorithms that are used to pick one of the sets
among a set-associative cache for replacement when conflict miss
occurs.
and all those speed/gatecount/area, i m not specific about any of
them right now. All i need is the best known implementation mechanism.
Have a look at Tomasz' reply, if that makes sense!
regards,
mnsharif
> invincible1138 wrote:
>
> >Hi all!
> >
> >I want to know the most optimal way to implement FIFO/LRU/Random
in
> >hardware. I am designing a cache and i need to implement these as
> >replacement algorithms. I guess this makes clear why i want a fast
> >hardware solution for implementing these.
> >
> >regards,
> >mnsharif
> >
> What type of fifo , which LRU , which random in what hardware ?
> For what purpose ?
>
> For what parameter ? speed , gate count , area , reliabilty ,
error
> checking ?
>
> Makes what clear ?
>
> Your post makes nothing clear
>
> Alex
Hey Alex,
By hardware i meant FPGA, offcourse i m not talking about PCB or ASIC
in fpga-cpu forum
By FIFO (first in first out), Random and LRU (least recently used) i
meant the replacemnt algorithms that are used to pick one of the sets
among a set-associative cache for replacement when conflict miss
occurs.
and all those speed/gatecount/area, i m not specific about any of
them right now. All i need is the best known implementation mechanism.
Have a look at Tomasz' reply, if that makes sense!
regards,
mnsharif
