Hello,
I came across this old posting for the POP-11, but the original
URL no longer works. I'd really like to get the
VHDL source code for the POP-11 project if possible.
Can someone send me an updated URL?
Thanks in Advance,
Scott
-- In Oct 6, 2004, Naohiko Shimizu-san wrote:
>
> Hi all,
>
> I and my student Mr.Iida placed a PDP11/40 compatible CPU source
> code on our web site. (POP11/40) That includes, CPU, serial
> interface and RK to IDE protocol converter.
>
> We used the processor with ALTERA's EP1C3 or EP1K100.
> Whole logic to boot UNIX V6 is fit within 3000 LUT on ALTERA.
>
> I hope you enjoy it.
>
> http://shimizu-lab.dt.u-tokai.ac.jp/pop11.html
>
> Naohiko Shimizu
>
POP-11 (PDP-11/40 in an FPGA)
Started by ●August 16, 2007
Reply by ●August 17, 20072007-08-17
Scott wrote:
> I came across this old posting for the POP-11, but the original
> URL no longer works. I'd really like to get the
> VHDL source code for the POP-11 project if possible.
> Can someone send me an updated URL?
It wasn't written in VHDL or Verilog. It was designed in sfl, then
compiled into Verilog using sfl2vl, a tool only available as a
Windows executable.
I haven't seen the output of sfl2vl, but I doubt that it was
very human-friendly.
> I came across this old posting for the POP-11, but the original
> URL no longer works. I'd really like to get the
> VHDL source code for the POP-11 project if possible.
> Can someone send me an updated URL?
It wasn't written in VHDL or Verilog. It was designed in sfl, then
compiled into Verilog using sfl2vl, a tool only available as a
Windows executable.
I haven't seen the output of sfl2vl, but I doubt that it was
very human-friendly.
Reply by ●August 18, 20072007-08-18
Hi Eric & Scott,
I found a link to the SFL to Verilog program, but it appears to be at
http://shimizu-lab.dt.u-tokai.ac.jp/pgm/sfl2vl/index.html
which is the same university as the POP11/40 and the link no longer works
Dr. Naohiko Shimizu seems to have set up a web site here:
http://www.ip-arch.jp/indexe.html
There is a not for profit version of his SFL to Verilog translator
but I can't see the POP11/40 design.
John.
Eric Smith wrote:
>
> Scott wrote:
> > I came across this old posting for the POP-11, but the original
> > URL no longer works. I'd really like to get the
> > VHDL source code for the POP-11 project if possible.
> > Can someone send me an updated URL?
>
> It wasn't written in VHDL or Verilog. It was designed in sfl, then
> compiled into Verilog using sfl2vl, a tool only available as a
> Windows executable.
>
> I haven't seen the output of sfl2vl, but I doubt that it was
> very human-friendly.
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
I found a link to the SFL to Verilog program, but it appears to be at
http://shimizu-lab.dt.u-tokai.ac.jp/pgm/sfl2vl/index.html
which is the same university as the POP11/40 and the link no longer works
Dr. Naohiko Shimizu seems to have set up a web site here:
http://www.ip-arch.jp/indexe.html
There is a not for profit version of his SFL to Verilog translator
but I can't see the POP11/40 design.
John.
Eric Smith wrote:
>
> Scott wrote:
> > I came across this old posting for the POP-11, but the original
> > URL no longer works. I'd really like to get the
> > VHDL source code for the POP-11 project if possible.
> > Can someone send me an updated URL?
>
> It wasn't written in VHDL or Verilog. It was designed in sfl, then
> compiled into Verilog using sfl2vl, a tool only available as a
> Windows executable.
>
> I haven't seen the output of sfl2vl, but I doubt that it was
> very human-friendly.
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
Reply by ●August 18, 20072007-08-18
Hi Eric,
SFL looks like an interesting language. I have the sfl2vl
tool installed, but I have not tried any test cases.
Do you know where I can find the POP-11 SFL source?
Regards,
Scott
--- In f..., "Eric Smith" wrote:
>
> It wasn't written in VHDL or Verilog. It was designed in sfl, then
> compiled into Verilog using sfl2vl, a tool only available as a
> Windows executable.
>
> I haven't seen the output of sfl2vl, but I doubt that it was
> very human-friendly.
>
SFL looks like an interesting language. I have the sfl2vl
tool installed, but I have not tried any test cases.
Do you know where I can find the POP-11 SFL source?
Regards,
Scott
--- In f..., "Eric Smith" wrote:
>
> It wasn't written in VHDL or Verilog. It was designed in sfl, then
> compiled into Verilog using sfl2vl, a tool only available as a
> Windows executable.
>
> I haven't seen the output of sfl2vl, but I doubt that it was
> very human-friendly.
>
Reply by ●August 21, 20072007-08-21
Hi,
Dr. Shimizu says that the website where the POP-11 source code
is located is down for maintenance and it will be available again
next week.
In the meantime, I have decided to write my own PDP-11 VHDL model
from scratch. I currently have completed the instruction decoder.
Regards,
Scott
Dr. Shimizu says that the website where the POP-11 source code
is located is down for maintenance and it will be available again
next week.
In the meantime, I have decided to write my own PDP-11 VHDL model
from scratch. I currently have completed the instruction decoder.
Regards,
Scott
Reply by ●August 21, 20072007-08-21
Hey John,
Cool. There is an email address for Dr. Shimizu at the bottom
of that page, so I have written to him asking if the POP-11
SFL code is still available. I had previously written to him
at his Tokai University address, but I received no response
from that address.
In the meantime, last night I sat down and wrote the VHDL
case statements for a PDP-11/40 instruction decoder.
So I am on my way to writing my own model :-)
I'll let you know how it goes.
Regards,
Scott L Baker
--- In f..., John Kent wrote:
>
> Hi Eric & Scott,
>
> I found a link to the SFL to Verilog program, but it appears to be at
>
> http://shimizu-lab.dt.u-tokai.ac.jp/pgm/sfl2vl/index.html
>
> which is the same university as the POP11/40 and the link no longer
works
>
> Dr. Naohiko Shimizu seems to have set up a web site here:
>
> http://www.ip-arch.jp/indexe.html
>
> There is a not for profit version of his SFL to Verilog translator
> but I can't see the POP11/40 design.
>
> John.
> --- In f..., "Scott" wrote:
>>
>> Hi Eric,
>>
>> SFL looks like an interesting language. I have the sfl2vl
>> tool installed, but I have not tried any test cases.
>> Do you know where I can find the POP-11 SFL source?
>>
>> Regards,
>> Scott
>>
Cool. There is an email address for Dr. Shimizu at the bottom
of that page, so I have written to him asking if the POP-11
SFL code is still available. I had previously written to him
at his Tokai University address, but I received no response
from that address.
In the meantime, last night I sat down and wrote the VHDL
case statements for a PDP-11/40 instruction decoder.
So I am on my way to writing my own model :-)
I'll let you know how it goes.
Regards,
Scott L Baker
--- In f..., John Kent wrote:
>
> Hi Eric & Scott,
>
> I found a link to the SFL to Verilog program, but it appears to be at
>
> http://shimizu-lab.dt.u-tokai.ac.jp/pgm/sfl2vl/index.html
>
> which is the same university as the POP11/40 and the link no longer
works
>
> Dr. Naohiko Shimizu seems to have set up a web site here:
>
> http://www.ip-arch.jp/indexe.html
>
> There is a not for profit version of his SFL to Verilog translator
> but I can't see the POP11/40 design.
>
> John.
> --- In f..., "Scott" wrote:
>>
>> Hi Eric,
>>
>> SFL looks like an interesting language. I have the sfl2vl
>> tool installed, but I have not tried any test cases.
>> Do you know where I can find the POP-11 SFL source?
>>
>> Regards,
>> Scott
>>
Reply by ●August 21, 20072007-08-21
--- In f..., "Scott" wrote:
>
> Hey John,
>
> Cool. There is an email address for Dr. Shimizu at the bottom
> of that page, so I have written to him asking if the POP-11
> SFL code is still available. I had previously written to him
> at his Tokai University address, but I received no response
> from that address.
>
> In the meantime, last night I sat down and wrote the VHDL
> case statements for a PDP-11/40 instruction decoder.
> So I am on my way to writing my own model :-)
> I'll let you know how it goes.
>
> Regards,
> Scott L Baker
I am interested in your project and would like to tag along. My first
question: is there a complete suite of software available for the CPU?
Please keep the group posted!
Richard
>
> Hey John,
>
> Cool. There is an email address for Dr. Shimizu at the bottom
> of that page, so I have written to him asking if the POP-11
> SFL code is still available. I had previously written to him
> at his Tokai University address, but I received no response
> from that address.
>
> In the meantime, last night I sat down and wrote the VHDL
> case statements for a PDP-11/40 instruction decoder.
> So I am on my way to writing my own model :-)
> I'll let you know how it goes.
>
> Regards,
> Scott L Baker
I am interested in your project and would like to tag along. My first
question: is there a complete suite of software available for the CPU?
Please keep the group posted!
Richard
Reply by ●August 21, 20072007-08-21
Richard,
On Tue, 2007-08-21 at 13:11 +0000, rtstofer wrote:
> I am interested in your project and would like to tag along. My first
> question: is there a complete suite of software available for the CPU?
you can run UNIX 7th Edition on a PDP-11/40. The original
distribution tape is available from http://www.tuhs.org
You must configure the software before you can use it on
an 11/40. This is best done on a running system. I have
V7 running on a simulator (I'm in the process of porting
it to my own 32-bit RISC CPU). All the software you need
(including V7 and the simulator) can be downloaded from
my site http://homepages.fh-giessen.de/~hg53/pdp11-unix
If you have any questions, feel free to ask.
Best regards,
Hellwig
On Tue, 2007-08-21 at 13:11 +0000, rtstofer wrote:
> I am interested in your project and would like to tag along. My first
> question: is there a complete suite of software available for the CPU?
you can run UNIX 7th Edition on a PDP-11/40. The original
distribution tape is available from http://www.tuhs.org
You must configure the software before you can use it on
an 11/40. This is best done on a running system. I have
V7 running on a simulator (I'm in the process of porting
it to my own 32-bit RISC CPU). All the software you need
(including V7 and the simulator) can be downloaded from
my site http://homepages.fh-giessen.de/~hg53/pdp11-unix
If you have any questions, feel free to ask.
Best regards,
Hellwig
Reply by ●August 21, 20072007-08-21
Hellwig,
Thanks for the links. I have absolutely NO experience with the PDP-11
so these links will give me a start.
Richard
Thanks for the links. I have absolutely NO experience with the PDP-11
so these links will give me a start.
Richard
Reply by ●August 21, 20072007-08-21
It's back! See http://shimizu-lab.dt.u-tokai.ac.jp/pop11.html
This time I'll download it and put it on a CD! Perhaps this winter
I'll get around to converting it to run on a Spartan 3 Starter Board.
If I read the info correctly, it was built on a chip with 100k gates
so a 1M gate Spartan 3 ought to work!
Richard
This time I'll download it and put it on a CD! Perhaps this winter
I'll get around to converting it to run on a Spartan 3 Starter Board.
If I read the info correctly, it was built on a chip with 100k gates
so a 1M gate Spartan 3 ought to work!
Richard
