Using DDR RAM

On Wed, 07 Oct 2009 00:15:10 +1100, you wrote:

>Jon, Richard, Hellwig, Andreas, and others,
>
>You might like to check out Henk Gooijen's PDP-11 web site. I think he
>might have been machining his own front panels ... I'm not 100% sure.
>
>http://www.pdp-11.nl/

Okay. Now I'm impressed I wonder if Henk would be interested in
adopting me! ;)

Jon


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--- On Sun, 10/4/09, John Kent wrote:
> > I was having a discussion with Tommy Thorn on this list back in April
> > this year about his MIPS compatible YARI CPU that used 4-way
> > associative instruction and data cache. That might give you some
> > design clues.
> >
> > http://yari.thorn.ws/YARI/Introduction.html
> >
> > I've seen very little activity on this list since then. I hope my
> > email address has been working.

Thanks for the pitch. I've been very busy since, but there are a few
changes in the "pipeline": SDRAM support for DE2-70 and SSRAM support
for ML-401.

There is definitely a lack of DDR controllers. This is truly a Frequently
Asked Question. A while back there was a posting of a port of an Open Cores DDR controller to one of the Digilent Spartan 3 boards. I got it
running on the Spartan 3S1600 board.

All modern dynamic RAM are designed for caches. The data cache and instruction cache in YARI should be fairly straight forward to follow, but they also aren't particularly sophisticated. In particular they:
- Use random replacement. There is a request for LRU replacement for real-
time reasons.
- Are write through caches. Implementing a write-back cache requires an
additional bitmap for dirty lines. (Also the line replacement policy
design space grows more interesting). I compensate partially by hac
- Waits for a full line before proceeding. Implementing critical word
first isn't complicated, but the extra tracking is likely to hurt
timing.

Tommy



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Tommy Thorn wrote:
> Thanks for the pitch. I've been very busy since, but there are a few
> changes in the "pipeline": SDRAM support for DE2-70 and SSRAM support
> for ML-401.
>
> There is definitely a lack of DDR controllers. This is truly a Frequently
> Asked Question. A while back there was a posting of a port of an Open Cores DDR controller to one of the Digilent Spartan 3 boards. I got it
> running on the Spartan 3S1600 board.
>
> All modern dynamic RAM are designed for caches. The data cache and instruction cache in YARI should be fairly straight forward to follow, but they also aren't particularly sophisticated. In particular they:
> - Use random replacement. There is a request for LRU replacement for real-
> time reasons.
> - Are write through caches. Implementing a write-back cache requires an
> additional bitmap for dirty lines. (Also the line replacement policy
> design space grows more interesting). I compensate partially by hac
> - Waits for a full line before proceeding. Implementing critical word
> first isn't complicated, but the extra tracking is likely to hurt
> timing.
>
> Tommy
>
Hi Tommy,

I saw the DE2-70 board on your web site. I hope to get to play with a
DE2-70 board shortly for some image processing applications. I've
downloaded a snap shot of your design files, so I might be able to try
it out soon.

Can you possible explain random replacement a little better and excuse
my ignorance, but what does LRU stand for ?

John.

--
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent



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--- In f..., John Kent wrote:
> Can you possible explain random replacement a little better and excuse
> my ignorance, but what does LRU stand for ?

What about :
http://en.wikipedia.org/wiki/Cache_algorithms



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--- On Thu, 10/8/09, e2kcpu wrote:

> From: e2kcpu
> Subject: [fpga-cpu] Re: Using DDR RAM
> To: f...
> Date: Thursday, October 8, 2009, 5:45 AM
> --- In f...,
> John Kent wrote:
> > Can you possible explain random replacement a little
> better and excuse
> > my ignorance, but what does LRU stand for ?
>
> What about :
> http://en.wikipedia.org/wiki/Cache_algorithms

That's technically accurate, but probably not meaningful without sufficient background.

John, I don't think I have enough time to do the topic justice. I strongly encourage you get the a copy of Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk
Seriously, this should be considered required reading for anyone on this list.

Of course, my replacement is only /pseudo-/random as I use the low two bits of a 10-bit LFSR, not all that random actually.

Cheers
Tommy



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e2kcpu wrote:
> --- In f..., John Kent wrote:
>
>> Can you possible explain random replacement a little better and excuse
>> my ignorance, but what does LRU stand for ?
>>
>
> What about :
> http://en.wikipedia.org/wiki/Cache_algorithms
>
>
Yep, Least Recently Used ...
Should have thought of that.

Thanks

John.

--
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent



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Tommy Thorn wrote:
> --- On Thu, 10/8/09, e2kcpu wrote:
>
>
>> From: e2kcpu
>>
>>
>> What about :
>> http://en.wikipedia.org/wiki/Cache_algorithms
>>
>
> That's technically accurate, but probably not meaningful without sufficient background.
>
> John, I don't think I have enough time to do the topic justice. I strongly encourage you get the a copy of Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk
> Seriously, this should be considered required reading for anyone on this list.
>
> Of course, my replacement is only /pseudo-/random as I use the low two bits of a 10-bit LFSR, not all that random actually.
>
> Cheers
> Tommy
>
Thanks Tommy,

My delay in responding is because I am working on a conference paper
that is over due, although developing effective caching techniques is an
important aspect of my research.

John.

--
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent



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Tommy Thorn wrote:
> --- On Thu, 10/8/09, e2kcpu wrote:
>
> That's technically accurate, but probably not meaningful without sufficient background.
>
> John, I don't think I have enough time to do the topic justice. I strongly encourage you get the a copy of Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk
> Seriously, this should be considered required reading for anyone on this list.
>
> Of course, my replacement is only /pseudo-/random as I use the low two bits of a 10-bit LFSR, not all that random actually.
>
> Cheers
> Tommy
>
I have seen that book, although I think my local bookshop might have had
difficulty in getting it in. I did buy "The Art of Multiprocessor
Programming" by Herlihy and Shavit, although that covers more
concurrency and interlocks than caching.

John.

--
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent



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The H&P is considered the "bible" of computer architecture. Amazon is your friend.
Tommy
--- On Fri, 10/9/09, John Kent wrote:

> From: John Kent
> Subject: Re: [fpga-cpu] Re: Using DDR RAM
> To: f...
> Date: Friday, October 9, 2009, 10:58 PM
>
>
> Tommy Thorn wrote:
> > --- On Thu, 10/8/09, e2kcpu
> wrote:
> >
> > That's technically accurate, but probably not
> meaningful without sufficient background.
> >
> > John, I don't think I have enough time to do the topic
> justice. I strongly encourage you get the a copy of
> Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk
> > Seriously, this should be considered required reading
> for anyone on this list.
> >
> > Of course, my replacement is only /pseudo-/random as I
> use the low two bits of a 10-bit LFSR, not all that random
> actually.
> >
> > Cheers
> > Tommy
> >
> I have seen that book, although I think my local bookshop
> might have had
> difficulty in getting it in. I did buy "The Art of
> Multiprocessor
> Programming" by Herlihy and Shavit, although that
> covers more
> concurrency and interlocks than caching.
>
> John.
>
> --
> http://www.johnkent.com.au
> http://members.optusnet.com.au/jekent
>
>
>
>
>
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>



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--- In f..., Tommy Thorn wrote:
>
> The H&P is considered the "bible" of computer architecture. Amazon is your friend.
> Tommy

Ordered last week. Should be here soon.

Richard



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