Hello Everyone.
well i have designed a system that contains
-- altera cyclone 3 FPGA, with 50M clock
-- altera epcs16 Flash (configuration device for cyclone3)
-- an LPC2468 ARM processor (running uLinux),
-- a 16M Synchronous DRAM (connected to FPGA and ARM)
-- rest the design has ethernet, usb memory device connector, FTDI interface,
JTAG interface, ETXexpress Connector for connection to x86 system via LPC,
GPIO's, multiple power-supplies.
so now i am working on a project to be developed on this design(VHDL based).
well the problem statement is to connect all 3 systems together using the
wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where
x86 and ARM share the same memory space and FPGA being the center part between
these two systems.
well whats done so far is the communication between x86 and FPGA via Wishbone
LPC interface and so connected to wishbone spi to ARM7, the wishbone interface
is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to
SPI-slave, and only one register has been shared between x86 and ARM to prove
the communication between x86 and ARM. Now the next step is to make certain
registers of x86 accessible to ARM over wishbone, this part would be the shared
memory part between x86 and ARM. what i propose is to have a dual port RAM
implementation on FPGA which then be connected to external RAM make x86 data
accessible to ARM.
well this is what i think, so anyone here has done this before over wishbone
interface? or may be without wishbone, i just need an idea that what i am doing
is going to right direction or not... also i am not sure about the Chip-Select
and Enable signals that will be handling the external memory access, if any idea
about that would be great.
thats all for now, if i get something further i will update.
looking forward for support from you all.
regards
Ammar
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FPGA to ARM7 shared memory concept via wishbone.
Started by ●August 23, 2010
Reply by ●August 23, 20102010-08-23
I can't say I completely understand what you are trying to do. The
Wishbone bus is intended for use within a system on chip design. I think all of
your pieces are external with their own bus. So to use the wishbone bus you
would need an ARM to wishbone interface, an x86 to wishbone interface and then a
memory to wishbone interface. Instead you can just use the memory as dual port
and design memory to ARM and x86 interfaces which would be much simpler.
I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
Rick
--- In f..., djammar@... wrote:
>
> Hello Everyone.
>
> well i have designed a system that contains
> -- altera cyclone 3 FPGA, with 50M clock
> -- altera epcs16 Flash (configuration device for cyclone3)
> -- an LPC2468 ARM processor (running uLinux),
> -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
>
> so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
>
> well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
>
> thats all for now, if i get something further i will update.
> looking forward for support from you all.
>
> regards
> Ammar
>
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
Rick
--- In f..., djammar@... wrote:
>
> Hello Everyone.
>
> well i have designed a system that contains
> -- altera cyclone 3 FPGA, with 50M clock
> -- altera epcs16 Flash (configuration device for cyclone3)
> -- an LPC2468 ARM processor (running uLinux),
> -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
>
> so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
>
> well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
>
> thats all for now, if i get something further i will update.
> looking forward for support from you all.
>
> regards
> Ammar
>
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
Reply by ●August 24, 20102010-08-24
Hi Rick,
well yes the use of wishbone is just as u said, but in my system i have other functioning modules on fpga as well, and i have now to integrate that core to x86 and ARM7, so this is the reason all have to be done over Wishbone.
well as i mention that ARM is operating uLinux so for the booting of Linux i need an external memory. well i try to explain it a bit briefly.
x86<----LPC----->[LPC wishbone controller slave]--{FPGA}--[SPI-slave-wishbone-controller]<------------SPI--------->ARM7-SPI-master
so, x86 can communicate with FPGA over LPC interface, where fpga contains a lpc slave module, which take action accordingly as the index addresses provided by lpc master,i.e. x86, e.g. access to certain register on fpga to store port80 data, or access to spi slave register to store lpc specific data or so...
where as ARM can also communicate to fpga via SPI interface, where fpga being spi-slave, in current core design arm can only communicate over spi, and get data from only the one specific register (i.e the lpc specific data register) and so is able to read the x86 data. but now what i want to do is that arm could read other data registers of lpc side aswell, like for instance it could be able to read the port80 register (already set on fpga), so for that i proposed a dual memory module in fpga, were the x86 side data be written there and being read by arm7 when required. but again, all have to be done over wishbone SoC.
Ammar
--- In f..., "gnuarm" wrote:
>
> I can't say I completely understand what you are trying to do. The Wishbone bus is intended for use within a system on chip design. I think all of your pieces are external with their own bus. So to use the wishbone bus you would need an ARM to wishbone interface, an x86 to wishbone interface and then a memory to wishbone interface. Instead you can just use the memory as dual port and design memory to ARM and x86 interfaces which would be much simpler.
>
> I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
>
> Rick
> --- In f..., djammar@ wrote:
> >
> > Hello Everyone.
> >
> > well i have designed a system that contains
> > -- altera cyclone 3 FPGA, with 50M clock
> > -- altera epcs16 Flash (configuration device for cyclone3)
> > -- an LPC2468 ARM processor (running uLinux),
> > -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> > -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
> >
> > so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
> >
> > well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> > well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
> >
> > thats all for now, if i get something further i will update.
> > looking forward for support from you all.
> >
> > regards
> > Ammar
>
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
well yes the use of wishbone is just as u said, but in my system i have other functioning modules on fpga as well, and i have now to integrate that core to x86 and ARM7, so this is the reason all have to be done over Wishbone.
well as i mention that ARM is operating uLinux so for the booting of Linux i need an external memory. well i try to explain it a bit briefly.
x86<----LPC----->[LPC wishbone controller slave]--{FPGA}--[SPI-slave-wishbone-controller]<------------SPI--------->ARM7-SPI-master
so, x86 can communicate with FPGA over LPC interface, where fpga contains a lpc slave module, which take action accordingly as the index addresses provided by lpc master,i.e. x86, e.g. access to certain register on fpga to store port80 data, or access to spi slave register to store lpc specific data or so...
where as ARM can also communicate to fpga via SPI interface, where fpga being spi-slave, in current core design arm can only communicate over spi, and get data from only the one specific register (i.e the lpc specific data register) and so is able to read the x86 data. but now what i want to do is that arm could read other data registers of lpc side aswell, like for instance it could be able to read the port80 register (already set on fpga), so for that i proposed a dual memory module in fpga, were the x86 side data be written there and being read by arm7 when required. but again, all have to be done over wishbone SoC.
Ammar
--- In f..., "gnuarm" wrote:
>
> I can't say I completely understand what you are trying to do. The Wishbone bus is intended for use within a system on chip design. I think all of your pieces are external with their own bus. So to use the wishbone bus you would need an ARM to wishbone interface, an x86 to wishbone interface and then a memory to wishbone interface. Instead you can just use the memory as dual port and design memory to ARM and x86 interfaces which would be much simpler.
>
> I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
>
> Rick
> --- In f..., djammar@ wrote:
> >
> > Hello Everyone.
> >
> > well i have designed a system that contains
> > -- altera cyclone 3 FPGA, with 50M clock
> > -- altera epcs16 Flash (configuration device for cyclone3)
> > -- an LPC2468 ARM processor (running uLinux),
> > -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> > -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
> >
> > so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
> >
> > well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> > well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
> >
> > thats all for now, if i get something further i will update.
> > looking forward for support from you all.
> >
> > regards
> > Ammar
>
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To unsubscribe, send a blank message to: f...
Reply by ●August 24, 20102010-08-24
Even I dont find use of Wishbone here.
U r trying to make communication form X86 to ARM through FPGA aren't u?
as Rick said every architecture has their BUS architecture. If you want to
make them talk each other
u just make them talk to ALTERA FPGA (X86- Altera & ARM (AMBA) -ALTERA)
and then create dual port memory in FPGA
which can be read by both but can be written by one at a time.
Altera system design tool (Xilinx EDK) must be designing system around fixed
bus architecture (likeXILINX use PLB4.6)
and they must be providing standard interface (Xilinx IPIF/ PLB4.6) for 3rd
party IP's like ARM and X86 to be integrated in their system.
To do this u dont need wishbone this is what I can say from whatever I have
understood.
And yes block diagram will really help to get clear picture.
Thank You,
Vishal Dharmadhikari
M.S. Computer Engineering
On Mon, Aug 23, 2010 at 5:02 AM, wrote:
> Hello Everyone.
>
> well i have designed a system that contains
> -- altera cyclone 3 FPGA, with 50M clock
> -- altera epcs16 Flash (configuration device for cyclone3)
> -- an LPC2468 ARM processor (running uLinux),
> -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> -- rest the design has ethernet, usb memory device connector, FTDI
> interface, JTAG interface, ETXexpress Connector for connection to x86 system
> via LPC, GPIO's, multiple power-supplies.
>
> so now i am working on a project to be developed on this design(VHDL
> based). well the problem statement is to connect all 3 systems together
> using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI)
> to ARM, where x86 and ARM share the same memory space and FPGA being the
> center part between these two systems.
>
> well whats done so far is the communication between x86 and FPGA via
> Wishbone LPC interface and so connected to wishbone spi to ARM7, the
> wishbone interface is implemented on FPGA, and in this part ARM is set to
> SPI master and FPGA to SPI-slave, and only one register has been shared
> between x86 and ARM to prove the communication between x86 and ARM. Now the
> next step is to make certain registers of x86 accessible to ARM over
> wishbone, this part would be the shared memory part between x86 and ARM.
> what i propose is to have a dual port RAM implementation on FPGA which then
> be connected to external RAM make x86 data accessible to ARM.
> well this is what i think, so anyone here has done this before over
> wishbone interface? or may be without wishbone, i just need an idea that
> what i am doing is going to right direction or not... also i am not sure
> about the Chip-Select and Enable signals that will be handling the external
> memory access, if any idea about that would be great.
>
> thats all for now, if i get something further i will update.
> looking forward for support from you all.
>
> regards
> Ammar
>
>
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
U r trying to make communication form X86 to ARM through FPGA aren't u?
as Rick said every architecture has their BUS architecture. If you want to
make them talk each other
u just make them talk to ALTERA FPGA (X86- Altera & ARM (AMBA) -ALTERA)
and then create dual port memory in FPGA
which can be read by both but can be written by one at a time.
Altera system design tool (Xilinx EDK) must be designing system around fixed
bus architecture (likeXILINX use PLB4.6)
and they must be providing standard interface (Xilinx IPIF/ PLB4.6) for 3rd
party IP's like ARM and X86 to be integrated in their system.
To do this u dont need wishbone this is what I can say from whatever I have
understood.
And yes block diagram will really help to get clear picture.
Thank You,
Vishal Dharmadhikari
M.S. Computer Engineering
On Mon, Aug 23, 2010 at 5:02 AM, wrote:
> Hello Everyone.
>
> well i have designed a system that contains
> -- altera cyclone 3 FPGA, with 50M clock
> -- altera epcs16 Flash (configuration device for cyclone3)
> -- an LPC2468 ARM processor (running uLinux),
> -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> -- rest the design has ethernet, usb memory device connector, FTDI
> interface, JTAG interface, ETXexpress Connector for connection to x86 system
> via LPC, GPIO's, multiple power-supplies.
>
> so now i am working on a project to be developed on this design(VHDL
> based). well the problem statement is to connect all 3 systems together
> using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI)
> to ARM, where x86 and ARM share the same memory space and FPGA being the
> center part between these two systems.
>
> well whats done so far is the communication between x86 and FPGA via
> Wishbone LPC interface and so connected to wishbone spi to ARM7, the
> wishbone interface is implemented on FPGA, and in this part ARM is set to
> SPI master and FPGA to SPI-slave, and only one register has been shared
> between x86 and ARM to prove the communication between x86 and ARM. Now the
> next step is to make certain registers of x86 accessible to ARM over
> wishbone, this part would be the shared memory part between x86 and ARM.
> what i propose is to have a dual port RAM implementation on FPGA which then
> be connected to external RAM make x86 data accessible to ARM.
> well this is what i think, so anyone here has done this before over
> wishbone interface? or may be without wishbone, i just need an idea that
> what i am doing is going to right direction or not... also i am not sure
> about the Chip-Select and Enable signals that will be handling the external
> memory access, if any idea about that would be great.
>
> thats all for now, if i get something further i will update.
> looking forward for support from you all.
>
> regards
> Ammar
>
>
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
Reply by ●August 24, 20102010-08-24
Ok, I understand better now. Part of my confusion was with the LPC interface.
I had not heard of that before and thought you were talking about an LPC ARM CPU
made by NXP. I found a reference that explains LPC as yet another bus created
by Intel for their CPUs. I guess it is a low speed interface, likely made for
controlling other chips on the Motherboard like their version of I2C which I
don't recall the name of.
From what you explain below, it sounds like you have a clear idea of how to proceed. The only issue that is not clear to me is how the SPI interface is converted to a wishbone interface. Is there a particular protocol for sending address, data and commands over SPI that this controller uses? SPI can easily be used to control a single register, but to control multiple registers requires that a protocol be added to SPI which has no default protocol for addressing registers. The default action of SPI is to treat all registers as being connected in series and for them all to be loaded in one long transfer.
How is the external memory connected to the ARM to run Linux? Normally external memory would be connected with a fast parallel bus. You aren't planning to access the external memory via SPI are you?
If the ARM interface only reads the LPC and other registers and doesn't write them, you don't need dual ported memory. You can have a million controllers reading the same register without any issues. It is only if more than one want to read the same registers that you need something special.
Rick
--- In f..., "Dark" wrote:
>
> Hi Rick,
>
> well yes the use of wishbone is just as u said, but in my system i have other functioning modules on fpga as well, and i have now to integrate that core to x86 and ARM7, so this is the reason all have to be done over Wishbone.
>
> well as i mention that ARM is operating uLinux so for the booting of Linux i need an external memory. well i try to explain it a bit briefly.
>
> x86<----LPC----->[LPC wishbone controller slave]--{FPGA}--[SPI-slave-wishbone-controller]<------------SPI--------->ARM7-SPI-master
>
> so, x86 can communicate with FPGA over LPC interface, where fpga contains a lpc slave module, which take action accordingly as the index addresses provided by lpc master,i.e. x86, e.g. access to certain register on fpga to store port80 data, or access to spi slave register to store lpc specific data or so...
> where as ARM can also communicate to fpga via SPI interface, where fpga being spi-slave, in current core design arm can only communicate over spi, and get data from only the one specific register (i.e the lpc specific data register) and so is able to read the x86 data. but now what i want to do is that arm could read other data registers of lpc side aswell, like for instance it could be able to read the port80 register (already set on fpga), so for that i proposed a dual memory module in fpga, were the x86 side data be written there and being read by arm7 when required. but again, all have to be done over wishbone SoC.
>
> Ammar
> --- In f..., "gnuarm" wrote:
> >
> > I can't say I completely understand what you are trying to do. The Wishbone bus is intended for use within a system on chip design. I think all of your pieces are external with their own bus. So to use the wishbone bus you would need an ARM to wishbone interface, an x86 to wishbone interface and then a memory to wishbone interface. Instead you can just use the memory as dual port and design memory to ARM and x86 interfaces which would be much simpler.
> >
> > I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
> >
> > Rick
> >
> >
> > --- In f..., djammar@ wrote:
> > >
> > > Hello Everyone.
> > >
> > > well i have designed a system that contains
> > > -- altera cyclone 3 FPGA, with 50M clock
> > > -- altera epcs16 Flash (configuration device for cyclone3)
> > > -- an LPC2468 ARM processor (running uLinux),
> > > -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> > > -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
> > >
> > > so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
> > >
> > > well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> > > well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
> > >
> > > thats all for now, if i get something further i will update.
> > > looking forward for support from you all.
> > >
> > > regards
> > > Ammar
> > >
>
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
From what you explain below, it sounds like you have a clear idea of how to proceed. The only issue that is not clear to me is how the SPI interface is converted to a wishbone interface. Is there a particular protocol for sending address, data and commands over SPI that this controller uses? SPI can easily be used to control a single register, but to control multiple registers requires that a protocol be added to SPI which has no default protocol for addressing registers. The default action of SPI is to treat all registers as being connected in series and for them all to be loaded in one long transfer.
How is the external memory connected to the ARM to run Linux? Normally external memory would be connected with a fast parallel bus. You aren't planning to access the external memory via SPI are you?
If the ARM interface only reads the LPC and other registers and doesn't write them, you don't need dual ported memory. You can have a million controllers reading the same register without any issues. It is only if more than one want to read the same registers that you need something special.
Rick
--- In f..., "Dark" wrote:
>
> Hi Rick,
>
> well yes the use of wishbone is just as u said, but in my system i have other functioning modules on fpga as well, and i have now to integrate that core to x86 and ARM7, so this is the reason all have to be done over Wishbone.
>
> well as i mention that ARM is operating uLinux so for the booting of Linux i need an external memory. well i try to explain it a bit briefly.
>
> x86<----LPC----->[LPC wishbone controller slave]--{FPGA}--[SPI-slave-wishbone-controller]<------------SPI--------->ARM7-SPI-master
>
> so, x86 can communicate with FPGA over LPC interface, where fpga contains a lpc slave module, which take action accordingly as the index addresses provided by lpc master,i.e. x86, e.g. access to certain register on fpga to store port80 data, or access to spi slave register to store lpc specific data or so...
> where as ARM can also communicate to fpga via SPI interface, where fpga being spi-slave, in current core design arm can only communicate over spi, and get data from only the one specific register (i.e the lpc specific data register) and so is able to read the x86 data. but now what i want to do is that arm could read other data registers of lpc side aswell, like for instance it could be able to read the port80 register (already set on fpga), so for that i proposed a dual memory module in fpga, were the x86 side data be written there and being read by arm7 when required. but again, all have to be done over wishbone SoC.
>
> Ammar
> --- In f..., "gnuarm" wrote:
> >
> > I can't say I completely understand what you are trying to do. The Wishbone bus is intended for use within a system on chip design. I think all of your pieces are external with their own bus. So to use the wishbone bus you would need an ARM to wishbone interface, an x86 to wishbone interface and then a memory to wishbone interface. Instead you can just use the memory as dual port and design memory to ARM and x86 interfaces which would be much simpler.
> >
> > I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
> >
> > Rick
> >
> >
> > --- In f..., djammar@ wrote:
> > >
> > > Hello Everyone.
> > >
> > > well i have designed a system that contains
> > > -- altera cyclone 3 FPGA, with 50M clock
> > > -- altera epcs16 Flash (configuration device for cyclone3)
> > > -- an LPC2468 ARM processor (running uLinux),
> > > -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> > > -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
> > >
> > > so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
> > >
> > > well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> > > well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
> > >
> > > thats all for now, if i get something further i will update.
> > > looking forward for support from you all.
> > >
> > > regards
> > > Ammar
> > >
>
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Reply by ●August 24, 20102010-08-24
Yes, its the Intel LPC, i think now that i would have mentioned that, any how.
well the standard spi interface has been modified according to the wishbone specifications, consider it as a module with two sides, one side connected to the spi master (ARM) with standard spi signals (MISO,MOSI,SSEL,SCLK) and the other side has been modified according to WB spec, and has been given an internal wishbone address and so become accessible over wishbone where these spi-slave registers are addressable now. and so, i can access the spi slave register form x86 side with an index address and then sending the data via intel-LPC, and that data is then registered to spi slave register, and then available for the serial transfer to spi master, in this way a low speed bus is connected to a high speed bus.
so i cannot send any control info form spi master(ARM) side, as if to ARM it is just a normal spi slave. well the other way is also there to use multiple spi slaves, i think 8 or 6 spi slaves are possible, but this approach is not good to follow, it cause lost of clock cycles, so this option has already been ruled out.
and yes by default spi can register only one register, and now the next step is exactly to develop something that either i can register multiple registers over spi, or may be any other way.
external 16M-Ram is connected to the standard address and data bus of ARM, and at boot, arm reads a boot-able usb flash drive, with a customized command eg 'run', it starts up the boot process, i.e. loads all the uLinux boot-loader, kernel and all the relevant files to ram and there of ARM only reads everything form this memory (no more usb drive required). so this is how its being connected and is used.
and no i am not planning to access this memory over spi. but i do think if i could load my other intel-LPC side register to specific address of this external ram so they become available for ARM to read :-)...
yes you are rite, but the dual port ram i designed here is like read and write able from LPC side and only readable form ARM side, but the issue is how ARM read this memory??? (also the standard data and address pins of ARM are also connected to FPGA as they are connected to external memory.so this makes the memory accessible for both arm and fpga or the other way around e.g. that arm can access a memory module implemented in fpga...
Ammar
--- In f..., "gnuarm" wrote:
>
> Ok, I understand better now. Part of my confusion was with the LPC interface. I had not heard of that before and thought you were talking about an LPC ARM CPU made by NXP. I found a reference that explains LPC as yet another bus created by Intel for their CPUs. I guess it is a low speed interface, likely made for controlling other chips on the Motherboard like their version of I2C which I don't recall the name of.
>
> From what you explain below, it sounds like you have a clear idea of how to proceed. The only issue that is not clear to me is how the SPI interface is converted to a wishbone interface. Is there a particular protocol for sending address, data and commands over SPI that this controller uses? SPI can easily be used to control a single register, but to control multiple registers requires that a protocol be added to SPI which has no default protocol for addressing registers. The default action of SPI is to treat all registers as being connected in series and for them all to be loaded in one long transfer.
>
> How is the external memory connected to the ARM to run Linux? Normally external memory would be connected with a fast parallel bus. You aren't planning to access the external memory via SPI are you?
>
> If the ARM interface only reads the LPC and other registers and doesn't write them, you don't need dual ported memory. You can have a million controllers reading the same register without any issues. It is only if more than one want to read the same registers that you need something special.
>
> Rick
> --- In f..., "Dark" wrote:
> >
> > Hi Rick,
> >
> > well yes the use of wishbone is just as u said, but in my system i have other functioning modules on fpga as well, and i have now to integrate that core to x86 and ARM7, so this is the reason all have to be done over Wishbone.
> >
> > well as i mention that ARM is operating uLinux so for the booting of Linux i need an external memory. well i try to explain it a bit briefly.
> >
> > x86<----LPC----->[LPC wishbone controller slave]--{FPGA}--[SPI-slave-wishbone-controller]<------------SPI--------->ARM7-SPI-master
> >
> > so, x86 can communicate with FPGA over LPC interface, where fpga contains a lpc slave module, which take action accordingly as the index addresses provided by lpc master,i.e. x86, e.g. access to certain register on fpga to store port80 data, or access to spi slave register to store lpc specific data or so...
> > where as ARM can also communicate to fpga via SPI interface, where fpga being spi-slave, in current core design arm can only communicate over spi, and get data from only the one specific register (i.e the lpc specific data register) and so is able to read the x86 data. but now what i want to do is that arm could read other data registers of lpc side aswell, like for instance it could be able to read the port80 register (already set on fpga), so for that i proposed a dual memory module in fpga, were the x86 side data be written there and being read by arm7 when required. but again, all have to be done over wishbone SoC.
> >
> > Ammar
> >
> >
> > --- In f..., "gnuarm" wrote:
> > >
> > > I can't say I completely understand what you are trying to do. The Wishbone bus is intended for use within a system on chip design. I think all of your pieces are external with their own bus. So to use the wishbone bus you would need an ARM to wishbone interface, an x86 to wishbone interface and then a memory to wishbone interface. Instead you can just use the memory as dual port and design memory to ARM and x86 interfaces which would be much simpler.
> > >
> > > I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
> > >
> > > Rick
> > >
> > >
> > > --- In f..., djammar@ wrote:
> > > >
> > > > Hello Everyone.
> > > >
> > > > well i have designed a system that contains
> > > > -- altera cyclone 3 FPGA, with 50M clock
> > > > -- altera epcs16 Flash (configuration device for cyclone3)
> > > > -- an LPC2468 ARM processor (running uLinux),
> > > > -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> > > > -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
> > > >
> > > > so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
> > > >
> > > > well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> > > > well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
> > > >
> > > > thats all for now, if i get something further i will update.
> > > > looking forward for support from you all.
> > > >
> > > > regards
> > > > Ammar
> > > >
> > >
>
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To unsubscribe, send a blank message to: f...
well the standard spi interface has been modified according to the wishbone specifications, consider it as a module with two sides, one side connected to the spi master (ARM) with standard spi signals (MISO,MOSI,SSEL,SCLK) and the other side has been modified according to WB spec, and has been given an internal wishbone address and so become accessible over wishbone where these spi-slave registers are addressable now. and so, i can access the spi slave register form x86 side with an index address and then sending the data via intel-LPC, and that data is then registered to spi slave register, and then available for the serial transfer to spi master, in this way a low speed bus is connected to a high speed bus.
so i cannot send any control info form spi master(ARM) side, as if to ARM it is just a normal spi slave. well the other way is also there to use multiple spi slaves, i think 8 or 6 spi slaves are possible, but this approach is not good to follow, it cause lost of clock cycles, so this option has already been ruled out.
and yes by default spi can register only one register, and now the next step is exactly to develop something that either i can register multiple registers over spi, or may be any other way.
external 16M-Ram is connected to the standard address and data bus of ARM, and at boot, arm reads a boot-able usb flash drive, with a customized command eg 'run', it starts up the boot process, i.e. loads all the uLinux boot-loader, kernel and all the relevant files to ram and there of ARM only reads everything form this memory (no more usb drive required). so this is how its being connected and is used.
and no i am not planning to access this memory over spi. but i do think if i could load my other intel-LPC side register to specific address of this external ram so they become available for ARM to read :-)...
yes you are rite, but the dual port ram i designed here is like read and write able from LPC side and only readable form ARM side, but the issue is how ARM read this memory??? (also the standard data and address pins of ARM are also connected to FPGA as they are connected to external memory.so this makes the memory accessible for both arm and fpga or the other way around e.g. that arm can access a memory module implemented in fpga...
Ammar
--- In f..., "gnuarm" wrote:
>
> Ok, I understand better now. Part of my confusion was with the LPC interface. I had not heard of that before and thought you were talking about an LPC ARM CPU made by NXP. I found a reference that explains LPC as yet another bus created by Intel for their CPUs. I guess it is a low speed interface, likely made for controlling other chips on the Motherboard like their version of I2C which I don't recall the name of.
>
> From what you explain below, it sounds like you have a clear idea of how to proceed. The only issue that is not clear to me is how the SPI interface is converted to a wishbone interface. Is there a particular protocol for sending address, data and commands over SPI that this controller uses? SPI can easily be used to control a single register, but to control multiple registers requires that a protocol be added to SPI which has no default protocol for addressing registers. The default action of SPI is to treat all registers as being connected in series and for them all to be loaded in one long transfer.
>
> How is the external memory connected to the ARM to run Linux? Normally external memory would be connected with a fast parallel bus. You aren't planning to access the external memory via SPI are you?
>
> If the ARM interface only reads the LPC and other registers and doesn't write them, you don't need dual ported memory. You can have a million controllers reading the same register without any issues. It is only if more than one want to read the same registers that you need something special.
>
> Rick
> --- In f..., "Dark" wrote:
> >
> > Hi Rick,
> >
> > well yes the use of wishbone is just as u said, but in my system i have other functioning modules on fpga as well, and i have now to integrate that core to x86 and ARM7, so this is the reason all have to be done over Wishbone.
> >
> > well as i mention that ARM is operating uLinux so for the booting of Linux i need an external memory. well i try to explain it a bit briefly.
> >
> > x86<----LPC----->[LPC wishbone controller slave]--{FPGA}--[SPI-slave-wishbone-controller]<------------SPI--------->ARM7-SPI-master
> >
> > so, x86 can communicate with FPGA over LPC interface, where fpga contains a lpc slave module, which take action accordingly as the index addresses provided by lpc master,i.e. x86, e.g. access to certain register on fpga to store port80 data, or access to spi slave register to store lpc specific data or so...
> > where as ARM can also communicate to fpga via SPI interface, where fpga being spi-slave, in current core design arm can only communicate over spi, and get data from only the one specific register (i.e the lpc specific data register) and so is able to read the x86 data. but now what i want to do is that arm could read other data registers of lpc side aswell, like for instance it could be able to read the port80 register (already set on fpga), so for that i proposed a dual memory module in fpga, were the x86 side data be written there and being read by arm7 when required. but again, all have to be done over wishbone SoC.
> >
> > Ammar
> >
> >
> > --- In f..., "gnuarm" wrote:
> > >
> > > I can't say I completely understand what you are trying to do. The Wishbone bus is intended for use within a system on chip design. I think all of your pieces are external with their own bus. So to use the wishbone bus you would need an ARM to wishbone interface, an x86 to wishbone interface and then a memory to wishbone interface. Instead you can just use the memory as dual port and design memory to ARM and x86 interfaces which would be much simpler.
> > >
> > > I don't understand how the external memory comes into all this. I think I am just not getting what you are describing. Maybe a block diagram would help. I don't see any use for the wishbone bus in any of this.
> > >
> > > Rick
> > >
> > >
> > > --- In f..., djammar@ wrote:
> > > >
> > > > Hello Everyone.
> > > >
> > > > well i have designed a system that contains
> > > > -- altera cyclone 3 FPGA, with 50M clock
> > > > -- altera epcs16 Flash (configuration device for cyclone3)
> > > > -- an LPC2468 ARM processor (running uLinux),
> > > > -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> > > > -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to x86 system via LPC, GPIO's, multiple power-supplies.
> > > >
> > > > so now i am working on a project to be developed on this design(VHDL based). well the problem statement is to connect all 3 systems together using the wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where x86 and ARM share the same memory space and FPGA being the center part between these two systems.
> > > >
> > > > well whats done so far is the communication between x86 and FPGA via Wishbone LPC interface and so connected to wishbone spi to ARM7, the wishbone interface is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to SPI-slave, and only one register has been shared between x86 and ARM to prove the communication between x86 and ARM. Now the next step is to make certain registers of x86 accessible to ARM over wishbone, this part would be the shared memory part between x86 and ARM. what i propose is to have a dual port RAM implementation on FPGA which then be connected to external RAM make x86 data accessible to ARM.
> > > > well this is what i think, so anyone here has done this before over wishbone interface? or may be without wishbone, i just need an idea that what i am doing is going to right direction or not... also i am not sure about the Chip-Select and Enable signals that will be handling the external memory access, if any idea about that would be great.
> > > >
> > > > thats all for now, if i get something further i will update.
> > > > looking forward for support from you all.
> > > >
> > > > regards
> > > > Ammar
> > > >
> > >
>
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