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I would like to use the XIRQ interrupt as a power loss detection. I have it connected to Vdd thru an external pull-up resistor. So whenever the power about to go out, I need to update 6 bytes of the Internal EEPROM. Appearantly, it is not working. The XIRQ does not detect when the power about to go out. Does anyone know on what voltage level will make the XIRQ go low? or how to make it recognize when there is a power interrupt? Please give me some input. Thanks alot guys. -Quyen |
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XIRQ
Started by ●July 16, 2004
Reply by ●July 16, 20042004-07-16
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In a message dated 7/16/04 4:44:46 PM Eastern Daylight Time, writes: I would like to use the XIRQ interrupt as a power loss detection. I have it connected to Vdd thru an external pull-up resistor. So whenever the power about to go out, I need to update 6 bytes of the Internal EEPROM. Appearantly, it is not working. The XIRQ does not detect when the power about to go out. Does anyone know on what voltage level will make the XIRQ go low? or how to make it recognize when there is a power interrupt? Please give me some input. Thanks alot guys. ===================================== To burn 6 bytes, you'll need a big cap that will hold up for 60ms or so driving the regulator... put a diode pointing to the big cap, and a smaller cap from the incoming voltage... lets say 12V.... now tie the xirq to the 12V thru a 7v zener... it will be 5v till the incoming voltage drops, but the big cap will still be at 12 for a while.... |
Reply by ●July 17, 20042004-07-17
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--- In , "quyenqtran" <quyenqtran@y...> wrote: > I would like to use the XIRQ interrupt as a power loss detection. > I have it connected to Vdd thru an external pull-up resistor. So > whenever the power about to go out, I need to update 6 bytes of > the Internal EEPROM. Appearantly, it is not working. The XIRQ does > not detect when the power about to go out. Does anyone know on > what voltage level will make the XIRQ go low? or how to make it > recognize when there is a power interrupt? Please give me some > input. Thanks alot guys. I have seen Bob Gardner's response to your message, and what he suggests will work under the correct conditions. My response will expand on what he said, and offer alternative approaches that you may find more flexible. There are at least three reasons that come to mind why your present approach is not working. First, the -XIRQ input responds to CMOS logic levels - typically 0.8*Vdd (4.0V) to be recognized as 'high' and 0.2*Vdd (1.0V) to be recognized as 'low'. Since the thresholds are based on the *present* voltage on Vdd, -XIRQ will never see a 'low' level, as the low-level trip threshold is constantly moving downward towards 0V as Vdd drops due to power loss. Even if the logic level thresholds were fixed (e.g. always 4.0V high/1.0V low regardless of Vdd level) the HC11 would stop operating properly well before Vdd fell below 1.0V; 3V is about the lowest Vdd that a HC11 can operate at. Finally, if your hardware incorporates a voltage detection IC or circuit for -RESET generation (such as the MC34064 3- pin reset generator), the CPU is going to get reset when Vdd falls below ~4.5V, and your XIRQ routine will never get executed even if - XIRQ eventually reaches the active level. Bob G.'s suggestion to use a 7V zener in a shunt regulator configuration tied to -XIRQ will work, but only if your power source to the board is very close to 12V. If it is higher, the zener you use will have to be increased (e.g. a 8.2V zener if your power source is 13.2V, or a 5.1V zener if your power source is 10V). If your incoming power source is not pre-regulated to a known, fixed voltage (before it is stepped down to 5V with another regulator or other means) then the zener-based detection method is not the best way to go. A better approach would be to use a voltage threshold detection device such as the MC34064 or equvalent. As I recall, these devices have a fixed 4.5V detection threshold - but you could use a simple resistor divider to 'scale' your input power source voltage level such that the voltage at the 'center' of the divider (that you route to the input of the threshold detection device) is always above 4.5V when the input supply voltage is at its nominal level. The output of the detector device would be tied (with a pullup resistor) to the -XIRQ input. The division ratio will need to be carefully selected to ensure that the center point never falls below 4.5V under any normal operating condition, such as a power surge that temporarily pulls the unregulated voltage level a bit lower than normal. As Bob G. noted, you will need to ensure that the Vdd source to the HC11 remains above 4.5V for long enough (after -XIRQ is triggered) to perform the EEPROM write operation, which will require 20mS * # bytes to update. You may be able to reduce this time if you reserve an entire 'row' of the internal EEPROM for your critical data, thus requiring only one row-erase cycle rather than an individual erase cycle for each byte. The time-per-byte will then drop to 10mS * #bytes plus a single fixed 10mS overhead to do the row erase. I have not tried using a row erase in any of my prior designs, so I'd have to research this more to give you specific details on how it is done. You can increase the time you have to do your power-fail routine if you shut down any power-consuming 'things' that are under control of the HC11, such as indicator LEDs. If you can reduce the load on the power supply to only that hardware that MUST remain operational during a power-fail scenario, you will reduce the load on the bulk caps in the power supply that are now your only source of power, thus increasing your up-time during a power failure. All of the approaches that I have discussed require that you are able to monitor a power source (that is directly related to the 5V source powering the HC11) that normally runs at a considerably higher voltage than 5V. This would be the case for a design that uses, say, a 12V unregulated DC source that is stepped down to 5V using a voltage regulator. If this is not the case - if your hardware does not have 'access' to this unregulated source - then the approaches discussed here will not be practical. One last thought on this subject. Monitoring DC voltage levels is not the only way to perform power fail detection. One method I used in a design some time ago used a retriggerable timer that was triggered by a zero-cross detector (with a lot of hysteresis) monitoring the *AC* waveform from the power supply step-down transformer. The output of the timer was tied to the -XIRQ input. The time-out on the timer was set to approx. 3 (U.S.) AC line cycles: 16.7 * 3 ~= 50 mS. If the timer timed out, it would be an indication that 3 or more AC line cycles were 'missing', a reasonable standard for power failure. As I recall, the AC-loss detector design mentioned above used a stage of a LM324 op-amp (in a comparator configuration) and a 4538 one-shot for the timer, along with a couple of resistors. Hope this helps. -- Mark Schultz |
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Reply by ●July 19, 20042004-07-19
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On Sun, 2004-07-18 at 11:59, Mark Schultz wrote: > Monitoring DC voltage levels is not the only way to perform > power fail detection. I was thinking along the same lines as I read the earlier posts. I would however go one stage further. Part of the ethic of microprocessors is to make the microprocessor do every last bit of the work, possible. In this case, the retriggerable timer is yet another part whose function should be performed by the µP. There are usually many reasons why you might want to keep in synchrony with the mains cycle in a mains-powered appliance, so having the XIRQ tied to (a threshold detector monitoring) the AC or fullwave-rectified output from the supply transformer becomes the simplest hardware solution. You will usually wish to implement a "software PLL" using a timer to account for mains glitches which may move or omit the synchronisation point, and the same PLL algorithm will provide detection of mains loss when three or four half-cycles are missed. > triggered by a zero-cross detector (with a lot of hysteresis) > monitoring the *AC* waveform from the power supply step-down > transformer. A symmetric, hysteretic zero-cross detector sounds an excellent way to provide threshold monitoring on both half-cycles. You need to do the calculations for any given design on what constitutes a "brownout" which will trigger the same defensive response. Brownouts are always nasty in computer systems. A power fail detector controlling reset at a threshold below the "warning" is probably necessary as well - under marginal conditions the µP will sense incipient power failure and save status, but continue to monitor power in "standby" until and unless a further criterion - perhaps several seconds of reliable mains cycles - is met to permit restoration of normal function. If however the brownout dips into region where µP operation to monitor this becomes untrustworthy, then it *is* shutdown by the primary power fail device. -- Cheers, Paul B. |
