Hello,

On SPI, is the shift register different than the data register? In 
other words, if I am a slave, can I put data in the SPI data register 
any time even while a transition is in progress? On PIC micros this is 
safe practice but what about LPC?

Thanks,

Gus
	

The SPI of the PICs is in my view superior of the one implemented in 
LPC. In LPC the maximum clock is lower (per Main clock) and you have no 
double buffering.

 From the User Manual:

/12.2.8 Write Collision
As stated previously, there is no write buffer between the SPI block bus 
interface, and the internal shift register. As a result, data must not 
be written to the SPI data register when a SPI data transfer is 
currently in progress. The time frame where data cannot be written to 
the SPI data register is from when the transfer starts, until after the 
status register has been read when the SPIF status is active. If the SPI 
data register is written in this time frame, the write data will be 
lost, and the write collision (WCOL) bit in the status register will be 
activated.
/
But I think that Philips knows that, because in the newer devices, one 
of the SPI is a SSP. And now you have not one 1 char in the buffer, but 8.
and the maximum clock rate is higher too (from 7.5Mhz to 30Mhz).

Mauricio
	Gus wrote:
> Hello,
>
> On SPI, is the shift register different than the data register? In
> other words, if I am a slave, can I put data in the SPI data register
> any time even while a transition is in progress? On PIC micros this is
> safe practice but what about LPC?
>
> Thanks,
>
> Gus
>
>
>
>
>
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> On SPI, is the shift register different than the data register? In
> other words, if I am a slave, can I put data in
the SPI data register
> any time even while a transition is in progress? On PIC micros this is
> safe practice but what about LPC?

SPI Data Register
User Manual excerpt:
"Writes to this register will be blocked from when a data transfer starts
to
when the SPIF status bit is set, and the status register has not been
read."

SSP port:
8 byte rx/tx FIFO, max speed is pclk/2.  You can fill FIFO at full speed,
refill from interrupt, or poll FIFO register for state change.
	Joel